cpu.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

    unsigned32 gpr1;	/* Stack pointer for all */
    unsigned32 gpr2;	/* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
    unsigned32 gpr13;	/* First non volatile PowerOpen, section ptr SVR4/EABI */
    unsigned32 gpr14;	/* Non volatile for all */
    unsigned32 gpr15;	/* Non volatile for all */
    unsigned32 gpr16;	/* Non volatile for all */
    unsigned32 gpr17;	/* Non volatile for all */
    unsigned32 gpr18;	/* Non volatile for all */
    unsigned32 gpr19;	/* Non volatile for all */
    unsigned32 gpr20;	/* Non volatile for all */
    unsigned32 gpr21;	/* Non volatile for all */
    unsigned32 gpr22;	/* Non volatile for all */
    unsigned32 gpr23;	/* Non volatile for all */
    unsigned32 gpr24;	/* Non volatile for all */
    unsigned32 gpr25;	/* Non volatile for all */
    unsigned32 gpr26;	/* Non volatile for all */
    unsigned32 gpr27;	/* Non volatile for all */
    unsigned32 gpr28;	/* Non volatile for all */
    unsigned32 gpr29;	/* Non volatile for all */
    unsigned32 gpr30;	/* Non volatile for all */
    unsigned32 gpr31;	/* Non volatile for all */
    unsigned32 cr;	/* PART of the CR is non volatile for all */
    unsigned32 pc;	/* Program counter/Link register */
    unsigned32 msr;	/* Initial interrupt level */
} Context_Control;

typedef struct {
    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
     * procedure calls.  However, this would mean that the interrupt
     * frame had to hold f0-f13, and the fpscr.  And as the majority
     * of tasks will not have an FP context, we will save the whole
     * context here.
     */
#if (PPC_HAS_DOUBLE == 1)
    double	f[32];
    double	fpscr;
#else
    float	f[32];
    float	fpscr;
#endif
} Context_Control_fp;

typedef struct CPU_Interrupt_frame {
    unsigned32 stacklink;	/* Ensure this is a real frame (also reg1 save) */
    unsigned32 calleeLr;	/* link register used by callees: SVR4/EABI */
  /* This is what is left out of the primary contexts */
    unsigned32 gpr0;
    unsigned32 gpr2;		/* play safe */
    unsigned32 gpr3;
    unsigned32 gpr4;
    unsigned32 gpr5;
    unsigned32 gpr6;
    unsigned32 gpr7;
    unsigned32 gpr8;
    unsigned32 gpr9;
    unsigned32 gpr10;
    unsigned32 gpr11;
    unsigned32 gpr12;
    unsigned32 gpr13;   /* Play safe */
    unsigned32 gpr28;   /* For internal use by the IRQ handler */
    unsigned32 gpr29;   /* For internal use by the IRQ handler */
    unsigned32 gpr30;   /* For internal use by the IRQ handler */
    unsigned32 gpr31;   /* For internal use by the IRQ handler */
    unsigned32 cr;	/* Bits of this are volatile, so no-one may save */
    unsigned32 ctr;
    unsigned32 xer;
    unsigned32 lr;
    unsigned32 pc;
    unsigned32 msr;
    unsigned32 pad[3];
} CPU_Interrupt_frame;
  
/*
 *  The following table contains the information required to configure
 *  the PowerPC processor specific parameters.
 */

typedef struct {
  void       (*pretasking_hook)( void );
  void       (*predriver_hook)( void );
  void       (*postdriver_hook)( void );
  void       (*idle_task)( void );
  boolean      do_zero_of_workspace;
  unsigned32   idle_task_stack_size;
  unsigned32   interrupt_stack_size;
  unsigned32   extra_mpci_receive_server_stack;
  void *     (*stack_allocate_hook)( unsigned32 );
  void       (*stack_free_hook)( void* );
  /* end of fields required on all CPUs */

  unsigned32   clicks_per_usec;	       /* Timer clicks per microsecond */
  boolean      exceptions_in_RAM;     /* TRUE if in RAM */

#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
  unsigned32   serial_per_sec;	       /* Serial clocks per second */
  boolean      serial_external_clock;
  boolean      serial_xon_xoff;
  boolean      serial_cts_rts;
  unsigned32   serial_rate;
  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
  unsigned32   timer_least_valid;      /* Least valid number from timer      */
  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
#endif

#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
  unsigned32   clock_speed;            /* Speed of CPU in Hz */
#endif
}   rtems_cpu_table;

/*
 *  Macros to access required entires in the CPU Table are in 
 *  the file rtems/system.h.
 */

/*
 *  Macros to access PowerPC MPC750 specific additions to the CPU Table
 */

#define rtems_cpu_configuration_get_clicks_per_usec() \
   (_CPU_Table.clicks_per_usec)

#define rtems_cpu_configuration_get_exceptions_in_ram() \
   (_CPU_Table.exceptions_in_RAM)

/*
 *  This variable is optional.  It is used on CPUs on which it is difficult
 *  to generate an "uninitialized" FP context.  It is filled in by
 *  _CPU_Initialize and copied into the task's FP context area during
 *  _CPU_Context_Initialize.
 */

/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */

/*
 *  On some CPUs, RTEMS supports a software managed interrupt stack.
 *  This stack is allocated by the Interrupt Manager and the switch
 *  is performed in _ISR_Handler.  These variables contain pointers
 *  to the lowest and highest addresses in the chunk of memory allocated
 *  for the interrupt stack.  Since it is unknown whether the stack
 *  grows up or down (in general), this give the CPU dependent
 *  code the option of picking the version it wants to use.
 *
 *  NOTE: These two variables are required if the macro
 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
 */

SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
SCORE_EXTERN void               *_CPU_Interrupt_stack_high;

#endif /* ndef ASM */

/*
 *  This defines the number of levels and the mask used to pick those
 *  bits out of a thread mode.
 */

#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */

/*
 *  With some compilation systems, it is difficult if not impossible to
 *  call a high-level language routine from assembly language.  This
 *  is especially true of commercial Ada compilers and name mangling
 *  C++ ones.  This variable can be optionally defined by the CPU porter
 *  and contains the address of the routine _Thread_Dispatch.  This
 *  can make it easier to invoke that routine at the end of the interrupt
 *  sequence (if a dispatch is necessary).
 */

/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */

/*
 *  Nothing prevents the porter from declaring more CPU specific variables.
 */

#ifndef ASM
  
SCORE_EXTERN struct {
  unsigned32 *Disable_level;
  void *Stack;
  volatile boolean *Switch_necessary;
  boolean *Signal;

} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;

#endif /* ndef ASM */

/*
 *  The size of the floating point context area.  On some CPUs this
 *  will not be a "sizeof" because the format of the floating point
 *  area is not defined -- only the size is.  This is usually on
 *  CPUs with a "floating point save context" instruction.
 */

#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

/*
 * (Optional) # of bytes for libmisc/stackchk to check
 * If not specifed, then it defaults to something reasonable
 * for most architectures.
 */

#define CPU_STACK_CHECK_SIZE    (128)

/*
 *  Amount of extra stack (above minimum stack size) required by
 *  MPCI receive server thread.  Remember that in a multiprocessor
 *  system this thread must exist and be able to process all directives.
 */

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

/*
 *  This defines the number of entries in the ISR_Vector_table managed
 *  by RTEMS.
 */

#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)

/*
 *  This is defined if the port has a special way to report the ISR nesting
 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
 *  being maintained (e.g. watchdog queues).
 */

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

/*
 *  Should be large enough to run all RTEMS tests.  This insures
 *  that a "reasonable" small application should not have any problems.
 */

#define CPU_STACK_MINIMUM_SIZE          (1024*8)

/*
 *  CPU's worst alignment requirement for data types on a byte boundary.  This
 *  alignment does not take into account the requirements for the stack.
 */

#define CPU_ALIGNMENT              (PPC_ALIGNMENT)

/*
 *  This number corresponds to the byte alignment requirement for the
 *  heap handler.  This alignment requirement may be stricter than that
 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
 *  common for the heap to follow the same alignment requirement as
 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
 *  then this should be set to CPU_ALIGNMENT.
 *
 *  NOTE:  This does not have to be a power of 2.  It does have to
 *         be greater or equal to than CPU_ALIGNMENT.
 */

#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)

/*
 *  This number corresponds to the byte alignment requirement for memory
 *  buffers allocated by the partition manager.  This alignment requirement
 *  may be stricter than that for the data types alignment specified by
 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
 *
 *  NOTE:  This does not have to be a power of 2.  It does have to
 *         be greater or equal to than CPU_ALIGNMENT.
 */

#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)

/*
 *  This number corresponds to the byte alignment requirement for the
 *  stack.  This alignment requirement may be stricter than that for the
 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
 *  is strict enough for the stack, then this should be set to 0.
 *
 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
 */

#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)

/*
 * Needed for Interrupt stack
 */
#define CPU_MINIMUM_STACK_FRAME_SIZE 8


/*
 *  ISR handler macros
 */

#define _CPU_Initialize_vectors()

/*
 *  Disable all interrupts for an RTEMS critical section.  The previous
 *  level is returned in _isr_cookie.
 */

#ifndef ASM
  
static inline unsigned32 _CPU_ISR_Get_level( void )
{
  register unsigned int msr;
  _CPU_MSR_GET(msr);
  if (msr & MSR_EE) return 0;
  else	return 1;
}

static inline void _CPU_ISR_Set_level( unsigned32 level )
{
  register unsigned int msr;
  _CPU_MSR_GET(msr);
  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
    msr |= MSR_EE;
  }
  else {
    msr &= ~MSR_EE;
  }