cpu.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

 * just follow the basic HPPA alignment for the heap and partition
 */

#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT

/*
 * HPPA stack is best when 64 byte aligned.
 */

#define CPU_STACK_ALIGNMENT        64

#ifndef ASM

/* macros */

/*
 *  ISR handler macros
 *
 *  These macros perform the following functions:
 *     + initialize the RTEMS vector table
 *     + disable all maskable CPU interrupts
 *     + restore previous interrupt level (enable)
 *     + temporarily restore interrupts (flash)
 *     + set a particular level
 */

/*
 *  Support routine to initialize the RTEMS vector table after it is allocated.
 */

#define _CPU_Initialize_vectors()

/* Disable interrupts; returning previous psw bits in _isr_level */

#define _CPU_ISR_Disable( _isr_level ) \
  do { \
         HPPA_ASM_RSM(HPPA_PSW_I, _isr_level);         \
         if (_isr_level & HPPA_PSW_I) _isr_level = 0;  \
         else                          _isr_level = 1; \
  } while(0)

/* Enable interrupts to previous level from _CPU_ISR_Disable
 * does not change 'level'
 */

#define _CPU_ISR_Enable( _isr_level )  \
  { \
        register int _ignore; \
        if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
        else                 HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
  }

/* restore, then disable interrupts; does not change level */
#define _CPU_ISR_Flash( _isr_level ) \
  { \
        if (_isr_level == 0) \
        { \
              register int _ignore;  \
              HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
              HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
        } \
  }

/*
 * Interrupt task levels
 *
 * Future scheme proposal
 *      level will be an index into a array.
 *      Each entry of array will be the interrupt bits
 *        enabled for that level.  There will be 32 bits of external
 *        interrupts (to be placed in EIEM) and some (optional) bsp
 *        specific bits
 *
 * For pixel flow this *may* mean something like:
 *      level 0:   all interrupts enabled (external + rhino)
 *      level 1:   rhino disabled
 *      level 2:   all io interrupts disabled (timer still enabled)
 *      level 7:   *ALL* disabled (timer disabled)
 */

/* set interrupts on or off; does not return new level */
#define _CPU_ISR_Set_level( new_level ) \
  { \
        volatile int ignore; \
        if ( new_level )  HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
        else              HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
  }

/* return current level */
unsigned32 _CPU_ISR_Get_level( void );

/* end of ISR handler macros */

/*
 *  Context handler macros
 *
 *  These macros perform the following functions:
 *     + initialize a context area
 *     + restart the current thread
 *     + calculate the initial pointer into a FP context area
 *     + initialize an FP context area
 *
 *  HPPA port adds two macros which hide the "indirectness" of the
 *  pointer passed the save/restore FP context assembly routines.
 */

#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                  _new_level, _entry_point, _is_fp ) \
  do { \
    unsigned32 _stack; \
    \
    (_the_context)->flags = 0xfeedf00d; \
    (_the_context)->pcoqfront = (unsigned32)(_entry_point); \
    (_the_context)->pcoqback  = (unsigned32)(_entry_point) + 4; \
    (_the_context)->pcsqfront = 0; \
    (_the_context)->pcsqback  = 0; \
    if ( (_new_level) ) \
        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
    else \
        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
    \
    _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
    _stack &= ~(CPU_STACK_ALIGNMENT - 1); \
    if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
       _stack += CPU_FRAME_SIZE; \
    \
    (_the_context)->sp = (_stack); \
    (_the_context)->gr27 = _CPU_Default_gr27; \
  } while (0)

#define _CPU_Context_Restart_self( _the_context ) \
    do { \
         _CPU_Context_restore( (_the_context) ); \
    } while (0)

#define _CPU_Context_Fp_start( _base, _offset ) \
   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )

#define _CPU_Context_Initialize_fp( _destination ) \
  do { \
    *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
  } while(0)

#define _CPU_Context_save_fp( _fp_context ) \
   _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )

#define _CPU_Context_restore_fp( _fp_context ) \
   _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )

/* end of Context handler macros */

/*
 *  Fatal Error manager macros
 *
 *  These macros perform the following functions:
 *    + disable interrupts and halt the CPU
 */

void    hppa_cpu_halt(unsigned32 the_error);
#define _CPU_Fatal_halt( _error ) \
    hppa_cpu_halt(_error)

/* end of Fatal Error manager macros */

/*
 *  Bitfield handler macros
 *
 *  These macros perform the following functions:
 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
 *
 *  NOTE:
 *
 *  The HPPA does not have a scan instruction.  This functionality
 *  is implemented in software.
 */

#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE

int hppa_rtems_ffs(unsigned int value);
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
    _output = hppa_rtems_ffs(_value)

/* end of Bitfield handler macros */

/*
 *  Priority handler macros
 *
 *  These macros perform the following functions:
 *    + return a mask with the bit for this major/minor portion of
 *      of thread priority set.
 *    + translate the bit number returned by "Bitfield_find_first_bit"
 *      into an index into the thread ready chain bit maps
 *
 *  Note: 255 is the lowest priority
 */

#define _CPU_Priority_Mask( _bit_number ) \
  ( 1 << (_bit_number) )

#define _CPU_Priority_bits_index( _priority ) \
  (_priority)

/* end of Priority handler macros */

/* functions */

/*
 *  _CPU_Initialize
 *
 *  This routine performs CPU dependent initialization.
 */

void _CPU_Initialize(
  rtems_cpu_table  *cpu_table,
  void      (*thread_dispatch)
);

/*
 *  _CPU_ISR_install_raw_handler
 *
 *  This routine installs a "raw" interrupt handler directly into the 
 *  processor's vector table.
 */
 
void _CPU_ISR_install_raw_handler(
  unsigned32  vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);

/*
 *  _CPU_ISR_install_vector
 *
 *  This routine installs an interrupt vector.
 */

void _CPU_ISR_install_vector(
  unsigned32  vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);

/*
 *  _CPU_Context_switch
 *
 *  This routine switches from the run context to the heir context.
 */

void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);

/*
 *  _CPU_Context_restore
 *
 *  This routine is generally used only to restart self in an
 *  efficient manner and avoid stack conflicts.
 */

void _CPU_Context_restore(
  Context_Control *new_context
);

/*
 *  _CPU_Save_float_context
 *
 *  This routine saves the floating point context passed to it.
 *
 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
 *         which dereferences the pointer before calling this.
 */

void _CPU_Save_float_context(
  Context_Control_fp *fp_context
);

/*
 *  _CPU_Restore_float_context
 *
 *  This routine restores the floating point context passed to it.
 *
 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
 *         which dereferences the pointer before calling this.
 */

void _CPU_Restore_float_context(
  Context_Control_fp *fp_context
);


/*
 * The raw interrupt handler for external interrupts
 */

extern void _Generic_ISR_Handler(
    void
);


/*  The following routine swaps the endian format of an unsigned int.
 *  It must be static so it can be referenced indirectly.
 */

static inline unsigned int
CPU_swap_u32(unsigned32 value)
{
  unsigned32 swapped;

  HPPA_ASM_SWAPBYTES(value, swapped);

  return( swapped );
}

#define CPU_swap_u16( value ) \
  (((value&0xff) << 8) | ((value >> 8)&0xff))

#endif   /* ! ASM */

#ifdef __cplusplus
}
#endif

#endif   /* ! __CPU_h */