cpu.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

    __MIPS_FPU_REGISTER_TYPE fp6;
    __MIPS_FPU_REGISTER_TYPE fp7;
    __MIPS_FPU_REGISTER_TYPE fp8;
    __MIPS_FPU_REGISTER_TYPE fp9;
    __MIPS_FPU_REGISTER_TYPE fp10;
    __MIPS_FPU_REGISTER_TYPE fp11;
    __MIPS_FPU_REGISTER_TYPE fp12;
    __MIPS_FPU_REGISTER_TYPE fp13;
    __MIPS_FPU_REGISTER_TYPE fp14;
    __MIPS_FPU_REGISTER_TYPE fp15;
    __MIPS_FPU_REGISTER_TYPE fp16;
    __MIPS_FPU_REGISTER_TYPE fp17;
    __MIPS_FPU_REGISTER_TYPE fp18;
    __MIPS_FPU_REGISTER_TYPE fp19;
    __MIPS_FPU_REGISTER_TYPE fp20;
    __MIPS_FPU_REGISTER_TYPE fp21;
    __MIPS_FPU_REGISTER_TYPE fp22;
    __MIPS_FPU_REGISTER_TYPE fp23;
    __MIPS_FPU_REGISTER_TYPE fp24;
    __MIPS_FPU_REGISTER_TYPE fp25;
    __MIPS_FPU_REGISTER_TYPE fp26;
    __MIPS_FPU_REGISTER_TYPE fp27;
    __MIPS_FPU_REGISTER_TYPE fp28;
    __MIPS_FPU_REGISTER_TYPE fp29;
    __MIPS_FPU_REGISTER_TYPE fp30;
    __MIPS_FPU_REGISTER_TYPE fp31;
    __MIPS_FPU_REGISTER_TYPE fpcs;
#endif
} Context_Control_fp;

/*
 *  This struct reflects the stack frame employed in ISR_Handler.  Note
 *  that the ISR routine save some of the registers to this frame for
 *  all interrupts and exceptions.  Other registers are saved only on
 *  exceptions, while others are not touched at all.  The untouched 
 *  registers are not normally disturbed by high-level language 
 *  programs so they can be accessed when required.
 *
 *  The registers and their ordering in this struct must directly
 *  correspond to the layout and ordering of * shown in iregdef.h,
 *  as cpu_asm.S uses those definitions to fill the stack frame.  
 *  This struct provides access to the stack frame for C code.
 *
 *  Similarly, this structure is used by debugger stubs and exception
 *  processing routines so be careful when changing the format.
 *
 *  NOTE: The comments with this structure and cpu_asm.S should be kept
 *        in sync.  When in doubt, look in the  code to see if the
 *        registers you're interested in are actually treated as expected.
 *        The order of the first portion of this structure follows the
 *        order of registers expected by gdb.
 */

typedef struct
{
  __MIPS_REGISTER_TYPE  r0;       /*  0 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  at;       /*  1 -- saved always */
  __MIPS_REGISTER_TYPE  v0;       /*  2 -- saved always */
  __MIPS_REGISTER_TYPE  v1;       /*  3 -- saved always */
  __MIPS_REGISTER_TYPE  a0;       /*  4 -- saved always */
  __MIPS_REGISTER_TYPE  a1;       /*  5 -- saved always */
  __MIPS_REGISTER_TYPE  a2;       /*  6 -- saved always */
  __MIPS_REGISTER_TYPE  a3;       /*  7 -- saved always */
  __MIPS_REGISTER_TYPE  t0;       /*  8 -- saved always */
  __MIPS_REGISTER_TYPE  t1;       /*  9 -- saved always */
  __MIPS_REGISTER_TYPE  t2;       /* 10 -- saved always */
  __MIPS_REGISTER_TYPE  t3;       /* 11 -- saved always */
  __MIPS_REGISTER_TYPE  t4;       /* 12 -- saved always */
  __MIPS_REGISTER_TYPE  t5;       /* 13 -- saved always */
  __MIPS_REGISTER_TYPE  t6;       /* 14 -- saved always */
  __MIPS_REGISTER_TYPE  t7;       /* 15 -- saved always */
  __MIPS_REGISTER_TYPE  s0;       /* 16 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s1;       /* 17 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s2;       /* 18 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s3;       /* 19 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s4;       /* 20 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s5;       /* 21 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s6;       /* 22 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  s7;       /* 23 -- saved on exceptions */
  __MIPS_REGISTER_TYPE  t8;       /* 24 -- saved always */
  __MIPS_REGISTER_TYPE  t9;       /* 25 -- saved always */
  __MIPS_REGISTER_TYPE  k0;       /* 26 -- NOT FILLED IN, kernel tmp reg */
  __MIPS_REGISTER_TYPE  k1;       /* 27 -- NOT FILLED IN, kernel tmp reg */
  __MIPS_REGISTER_TYPE  gp;       /* 28 -- saved always */
  __MIPS_REGISTER_TYPE  sp;       /* 29 -- saved on exceptions NOT RESTORED */
  __MIPS_REGISTER_TYPE  fp;       /* 30 -- saved always */
  __MIPS_REGISTER_TYPE  ra;       /* 31 -- saved always */
  __MIPS_REGISTER_TYPE  c0_sr;    /* 32 -- saved always, some bits are */
                                  /*    manipulated per-thread          */
  __MIPS_REGISTER_TYPE  mdlo;     /* 33 -- saved always */
  __MIPS_REGISTER_TYPE  mdhi;     /* 34 -- saved always */
  __MIPS_REGISTER_TYPE  badvaddr; /* 35 -- saved on exceptions, read-only */
  __MIPS_REGISTER_TYPE  cause;    /* 36 -- saved on exceptions NOT restored */
  __MIPS_REGISTER_TYPE  epc;      /* 37 -- saved always, read-only register */
                                  /*        but logically restored */
  __MIPS_FPU_REGISTER_TYPE f0;    /* 38 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f1;    /* 39 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f2;    /* 40 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f3;    /* 41 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f4;    /* 42 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f5;    /* 43 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f6;    /* 44 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f7;    /* 45 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f8;    /* 46 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f9;    /* 47 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f10;   /* 48 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f11;   /* 49 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f12;   /* 50 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f13;   /* 51 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f14;   /* 52 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f15;   /* 53 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f16;   /* 54 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f17;   /* 55 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f18;   /* 56 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f19;   /* 57 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f20;   /* 58 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f21;   /* 59 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f22;   /* 60 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f23;   /* 61 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f24;   /* 62 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f25;   /* 63 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f26;   /* 64 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f27;   /* 65 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f28;   /* 66 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f29;   /* 67 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f30;   /* 68 -- saved if FP enabled */
  __MIPS_FPU_REGISTER_TYPE f31;   /* 69 -- saved if FP enabled */
  __MIPS_REGISTER_TYPE     fcsr;  /* 70 -- saved on exceptions */
                                  /*    (oddly not documented on MGV) */
  __MIPS_REGISTER_TYPE     feir;  /* 71 -- saved on exceptions */
                                  /*    (oddly not documented on MGV) */

  /* GDB does not seem to care about anything past this point */

  __MIPS_REGISTER_TYPE  tlbhi;    /* 72 - NOT FILLED IN, doesn't exist on */
                                  /*         all MIPS CPUs (at least MGV) */
#if __mips == 1
  __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
                                  /*         all MIPS CPUs (at least MGV) */
#endif
#if  __mips == 3
  __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
                                  /*         all MIPS CPUs (at least MGV) */
#endif

  __MIPS_REGISTER_TYPE  inx;      /* 74 -- NOT FILLED IN, doesn't exist on */
                                  /*         all MIPS CPUs (at least MGV) */
  __MIPS_REGISTER_TYPE  rand;     /* 75 -- NOT FILLED IN, doesn't exist on */
                                  /*         all MIPS CPUs (at least MGV) */
  __MIPS_REGISTER_TYPE  ctxt;     /* 76 -- NOT FILLED IN, doesn't exist on */
                                  /*         all MIPS CPUs (at least MGV) */
  __MIPS_REGISTER_TYPE  exctype;  /* 77 -- NOT FILLED IN (not enough info) */
  __MIPS_REGISTER_TYPE  mode;     /* 78 -- NOT FILLED IN (not enough info) */
  __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
  __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
  /* end of __mips == 1 so NREGS == 81 */
#if  __mips == 3
  __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  count;    /* 84 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  compare;  /* 85 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  config;   /* 86 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  lladdr;   /* 87 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  watchlo;  /* 88 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  watchhi;  /* 89 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  ecc;      /* 90 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  cacheerr; /* 91 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  taglo;    /* 92 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  taghi;    /* 93 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  errpc;    /* 94 -- NOT FILLED IN */
  __MIPS_REGISTER_TYPE  xctxt;    /* 95 -- NOT FILLED IN */
 /* end of __mips == 3 so NREGS == 96 */
#endif

} CPU_Interrupt_frame;


/*
 *  The following table contains the information required to configure
 *  the mips processor specific parameters.
 */

typedef struct {
  void       (*pretasking_hook)( void );
  void       (*predriver_hook)( void );
  void       (*postdriver_hook)( void );
  void       (*idle_task)( void );
  boolean      do_zero_of_workspace;
  unsigned32   idle_task_stack_size;
  unsigned32   interrupt_stack_size;
  unsigned32   extra_mpci_receive_server_stack;
  void *     (*stack_allocate_hook)( unsigned32 );
  void       (*stack_free_hook)( void* );
  /* end of fields required on all CPUs */

  unsigned32   clicks_per_microsecond;
}   rtems_cpu_table;


/*
 *  Macros to access required entires in the CPU Table are in
 *  the file rtems/system.h.
 */

/*
 *  Macros to access MIPS specific additions to the CPU Table
 */

#define rtems_cpu_configuration_get_clicks_per_microsecond() \
   (_CPU_Table.clicks_per_microsecond)

/*
 *  This variable is optional.  It is used on CPUs on which it is difficult
 *  to generate an "uninitialized" FP context.  It is filled in by
 *  _CPU_Initialize and copied into the task's FP context area during
 *  _CPU_Context_Initialize.
 */

SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;

/*
 *  On some CPUs, RTEMS supports a software managed interrupt stack.
 *  This stack is allocated by the Interrupt Manager and the switch
 *  is performed in _ISR_Handler.  These variables contain pointers
 *  to the lowest and highest addresses in the chunk of memory allocated
 *  for the interrupt stack.  Since it is unknown whether the stack
 *  grows up or down (in general), this give the CPU dependent
 *  code the option of picking the version it wants to use.
 *
 *  NOTE: These two variables are required if the macro
 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
 */

SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
SCORE_EXTERN void               *_CPU_Interrupt_stack_high;

/*
 *  With some compilation systems, it is difficult if not impossible to
 *  call a high-level language routine from assembly language.  This
 *  is especially true of commercial Ada compilers and name mangling
 *  C++ ones.  This variable can be optionally defined by the CPU porter
 *  and contains the address of the routine _Thread_Dispatch.  This
 *  can make it easier to invoke that routine at the end of the interrupt
 *  sequence (if a dispatch is necessary).
 *

SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
 *
 *  NOTE: Not needed on this port.
 */



/*
 *  Nothing prevents the porter from declaring more CPU specific variables.
 */

/* XXX: if needed, put more variables here */

/*
 *  The size of the floating point context area.  On some CPUs this
 *  will not be a "sizeof" because the format of the floating point
 *  area is not defined -- only the size is.  This is usually on
 *  CPUs with a "floating point save context" instruction.
 */

#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

/*
 *  Amount of extra stack (above minimum stack size) required by
 *  system initialization thread.  Remember that in a multiprocessor
 *  system the system intialization thread becomes the MP server thread.
 */

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

/*
 *  This defines the number of entries in the ISR_Vector_table managed
 *  by RTEMS.
 */

extern unsigned int mips_interrupt_number_of_vectors;
#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)

/*
 *  Should be large enough to run all RTEMS tests.  This insures
 *  that a "reasonable" small application should not have any problems.
 */

#define CPU_STACK_MINIMUM_SIZE          (2048*sizeof(unsigned32))


/*
 *  CPU's worst alignment requirement for data types on a byte boundary.  This
 *  alignment does not take into account the requirements for the stack.
 */

#define CPU_ALIGNMENT              8

/*
 *  This number corresponds to the byte alignment requirement for the
 *  heap handler.  This alignment requirement may be stricter than that
 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
 *  common for the heap to follow the same alignment requirement as
 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
 *  then this should be set to CPU_ALIGNMENT.
 *
 *  NOTE:  This does not have to be a power of 2.  It does have to
 *         be greater or equal to than CPU_ALIGNMENT.
 */

#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT

/*
 *  This number corresponds to the byte alignment requirement for memory
 *  buffers allocated by the partition manager.  This alignment requirement
 *  may be stricter than that for the data types alignment specified by
 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
 *
 *  NOTE:  This does not have to be a power of 2.  It does have to
 *         be greater or equal to than CPU_ALIGNMENT.
 */

#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT

/*
 *  This number corresponds to the byte alignment requirement for the
 *  stack.  This alignment requirement may be stricter than that for the
 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
 *  is strict enough for the stack, then this should be set to 0.
 *
 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
 */

#define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT

/*
 *  ISR handler macros
 */

/*
 *  Support routine to initialize the RTEMS vector table after it is allocated.
 */

#define _CPU_Initialize_vectors()

/*
 *  Disable all interrupts for an RTEMS critical section.  The previous
 *  level is returned in _level.
 */

#define _CPU_ISR_Disable( _level ) \
  do { \
    unsigned int _scratch; \
    mips_get_sr( _scratch ); \
    mips_set_sr( _scratch & ~SR_INTERRUPT_ENABLE_BITS ); \
    _level = _scratch & SR_INTERRUPT_ENABLE_BITS; \
  } while(0)

/*
 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
 *  This indicates the end of an RTEMS critical section.  The parameter
 *  _level is not modified.
 */

#define _CPU_ISR_Enable( _level )  \
  do { \
    unsigned int _scratch; \
    mips_get_sr( _scratch ); \
    mips_set_sr( (_scratch & ~SR_INTERRUPT_ENABLE_BITS) | (_level & SR_INTERRUPT_ENABLE_BITS) ); \
  } while(0)

/*
 *  This temporarily restores the interrupt to _level before immediately
 *  disabling them again.  This is used to divide long RTEMS critical
 *  sections into two or more parts.  The parameter _level is not
 *  modified.
 */

#define _CPU_ISR_Flash( _xlevel ) \
  do { \
    unsigned int _scratch2 = _xlevel; \
    _CPU_ISR_Enable( _scratch2 ); \
    _CPU_ISR_Disable( _scratch2 ); \
    _xlevel = _scratch2; \
  } while(0)

/*
 *  Map interrupt level in task mode onto the hardware that the CPU
 *  actually provides.  Currently, interrupt levels which do not
 *  map onto the CPU in a generic fashion are undefined.  Someday,
 *  it would be nice if these were "mapped" by the application
 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
 *  8 - 255 would be available for bsp/application specific meaning.
 *  This could be used to manage a programmable interrupt controller
 *  via the rtems_task_mode directive.
 *
 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only