idtcpu.h

RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating sys

#define	TLBINX_PROBE	0x80000000
#define	TLBINX_INXMASK	0x0000003f

#define	TLBRAND_RANDMASK	0x0000003f

#define	TLBCTXT_BASEMASK	0xff800000
#define	TLBCTXT_BASESHIFT	23

#define	TLBCTXT_VPN2MASK	0x007ffff0
#define	TLBCTXT_VPN2SHIFT	4

#define TLBPGMASK_MASK		0x01ffe000
#endif

#if  __mips == 1


/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
#define DCIC_TR		0x80000000	/* Trap enable */
#define DCIC_UD		0x40000000	/* User debug enable */
#define DCIC_KD		0x20000000	/* Kernel debug enable */
#define DCIC_TE		0x10000000	/* Trace enable */
#define DCIC_DW		0x08000000	/* Enable data breakpoints on write */
#define DCIC_DR		0x04000000	/* Enable data breakpoints on read */
#define DCIC_DAE	0x02000000	/* Enable data addresss breakpoints */
#define DCIC_PCE	0x01000000	/* Enable instruction breakpoints */
#define DCIC_DE		0x00800000	/* Debug enable */
#define DCIC_DL		0x00008000	/* Data cache line invalidate */
#define DCIC_IL		0x00004000	/* Instruction cache line invalidate */
#define DCIC_D		0x00002000	/* Data cache invalidate enable */
#define DCIC_I		0x00001000	/* Instr. cache invalidate enable */
#define DCIC_T		0x00000020	/* Trace, set by CPU */
#define DCIC_W		0x00000010	/* Write reference, set by CPU */
#define DCIC_R		0x00000008	/* Read reference, set by CPU */
#define DCIC_DA		0x00000004	/* Data address, set by CPU */
#define DCIC_PC		0x00000002	/* Program counter, set by CPU */
#define DCIC_DB		0x00000001	/* Debug, set by CPU */




#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */

#define	SR_BEV		0x00400000	/* use boot exception vectors */

/* Cache control bits */
#define	SR_TS		0x00200000	/* TLB shutdown */
#define	SR_PE		0x00100000	/* cache parity error */
#define	SR_CM		0x00080000	/* cache miss */
#define	SR_PZ		0x00040000	/* cache parity zero */
#define	SR_SWC		0x00020000	/* swap cache */
#define	SR_ISC		0x00010000	/* Isolate data cache */

/*
**	status register interrupt masks and bits
*/

#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
#define	SR_IMASK8	0x00000000	/* mask level 8 */
#define	SR_IMASK7	0x00008000	/* mask level 7 */
#define	SR_IMASK6	0x0000c000	/* mask level 6 */
#define	SR_IMASK5	0x0000e000	/* mask level 5 */
#define	SR_IMASK4	0x0000f000	/* mask level 4 */
#define	SR_IMASK3	0x0000f800	/* mask level 3 */
#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
#define	SR_IMASK0	0x0000ff00	/* mask level 0 */

#define	SR_IMASKSHIFT	8

#define	SR_IBIT8	0x00008000	/* bit level 8 */
#define	SR_IBIT7	0x00004000	/* bit level 7 */
#define	SR_IBIT6	0x00002000	/* bit level 6 */
#define	SR_IBIT5	0x00001000	/* bit level 5 */
#define	SR_IBIT4	0x00000800	/* bit level 4 */
#define	SR_IBIT3	0x00000400	/* bit level 3 */
#define	SR_IBIT2	0x00000200	/* bit level 2 */
#define	SR_IBIT1	0x00000100	/* bit level 1 */

#define	SR_KUO		0x00000020	/* old kernel/user, 0 => k, 1 => u */
#define	SR_IEO		0x00000010	/* old interrupt enable, 1 => enable */
#define	SR_KUP		0x00000008	/* prev kernel/user, 0 => k, 1 => u */
#define	SR_IEP		0x00000004	/* prev interrupt enable, 1 => enable */
#define	SR_KUC		0x00000002	/* cur kernel/user, 0 => k, 1 => u */
#define	SR_IEC		0x00000001	/* cur interrupt enable, 1 => enable */
#endif

#if  __mips == 3
#define	SR_CUMASK	0xf0000000	/* coproc usable bits */
#define	SR_CU3		0x80000000	/* Coprocessor 3 usable */
#define	SR_CU2		0x40000000	/* Coprocessor 2 usable */
#define	SR_CU1		0x20000000	/* Coprocessor 1 usable */
#define	SR_CU0		0x10000000	/* Coprocessor 0 usable */

#define SR_RP		0x08000000      /* Reduced power operation */
#define SR_FR		0x04000000	/* Additional floating point registers */
#define SR_RE		0x02000000	/* Reverse endian in user mode */

#define SR_BEV		0x00400000	/* Use boot exception vectors */
#define SR_TS		0x00200000	/* TLB shutdown */
#define SR_SR		0x00100000	/* Soft reset */
#define SR_CH		0x00040000	/* Cache hit */
#define SR_CE		0x00020000	/* Use cache ECC  */
#define SR_DE		0x00010000	/* Disable cache exceptions */

/*
**	status register interrupt masks and bits
*/

#define	SR_IMASK	0x0000ff00	/* Interrupt mask */
#define	SR_IMASK8	0x00000000	/* mask level 8 */
#define	SR_IMASK7	0x00008000	/* mask level 7 */
#define	SR_IMASK6	0x0000c000	/* mask level 6 */
#define	SR_IMASK5	0x0000e000	/* mask level 5 */
#define	SR_IMASK4	0x0000f000	/* mask level 4 */
#define	SR_IMASK3	0x0000f800	/* mask level 3 */
#define	SR_IMASK2	0x0000fc00	/* mask level 2 */
#define	SR_IMASK1	0x0000fe00	/* mask level 1 */
#define	SR_IMASK0	0x0000ff00	/* mask level 0 */

#define	SR_IMASKSHIFT	8

#define	SR_IBIT8	0x00008000	/* bit level 8 */
#define	SR_IBIT7	0x00004000	/* bit level 7 */
#define	SR_IBIT6	0x00002000	/* bit level 6 */
#define	SR_IBIT5	0x00001000	/* bit level 5 */
#define	SR_IBIT4	0x00000800	/* bit level 4 */
#define	SR_IBIT3	0x00000400	/* bit level 3 */
#define	SR_IBIT2	0x00000200	/* bit level 2 */
#define	SR_IBIT1	0x00000100	/* bit level 1 */

#define SR_KSMASK	0x00000018	/* Kernel mode mask */
#define SR_KSUSER	0x00000010	/* User mode */
#define SR_KSSUPER	0x00000008	/* Supervisor mode */
#define SR_KSKERNEL	0x00000000	/* Kernel mode */
#define SR_ERL		0x00000004	/* Error level */
#define SR_EXL		0x00000002	/* Exception level */
#define SR_IE		0x00000001	/* Interrupts enabled */
#endif



/*
 * Cause Register
 */
#define	CAUSE_BD	0x80000000	/* Branch delay slot */
#define	CAUSE_BT	0x40000000	/* Branch Taken */
#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
#define	CAUSE_CESHIFT	28


#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
#define	CAUSE_IPSHIFT	8

#define	CAUSE_EXCMASK	0x0000003C	/* Cause code bits */
#define	CAUSE_EXCSHIFT	2

#ifndef XDS
/*
**  Coprocessor 0 registers
*/
#define	C0_INX		$0		/* tlb index */
#define	C0_RAND		$1		/* tlb random */
#if  __mips == 1
#define	C0_TLBLO	$2		/* tlb entry low */
#endif
#if  __mips == 3
#define	C0_TLBLO0	$2		/* tlb entry low 0 */
#define	C0_TLBLO1	$3		/* tlb entry low 1 */
#endif

#define	C0_CTXT		$4		/* tlb context */

#if  __mips == 3
#define C0_PAGEMASK	$5		/* tlb page mask */
#define C0_WIRED	$6		/* number of wired tlb entries */
#endif

#if  __mips == 1
#define C0_TAR          $6
#endif

#define	C0_BADVADDR	$8		/* bad virtual address */

#if  __mips == 3
#define C0_COUNT	$9		/* cycle count */
#endif

#define	C0_TLBHI	$10		/* tlb entry hi */

#if  __mips == 3
#define C0_COMPARE	$11		/* cyccle count comparator  */
#endif

#define	C0_SR		$12		/* status register */
#define	C0_CAUSE	$13		/* exception cause */
#define	C0_EPC		$14		/* exception pc */
#define	C0_PRID		$15		/* revision identifier */

#if  __mips == 1
#define C0_CONFIG   $3     /* configuration register R3081*/
#endif

#if  __mips == 3
#define C0_CONFIG	$16		/* configuration register */
#define C0_LLADDR	$17		/* linked load address */
#define C0_WATCHLO	$18		/* watchpoint trap register */
#define C0_WATCHHI	$19		/* watchpoint trap register */
#define C0_XCTXT    $20     /* extended tlb context */
#define C0_ECC		$26		/* secondary cache ECC control */
#define C0_CACHEERR	$27		/* cache error status */
#define C0_TAGLO	$28		/* cache tag lo */
#define C0_TAGHI	$29		/* cache tag hi */
#define C0_ERRPC	$30		/* cache error pc */
#endif

#define C1_REVISION     $0
#define C1_STATUS       $31

#endif /* XDS */

#ifdef R4650
#define IWATCH $18
#define DWATCH $19
#define IBASE  $0
#define IBOUND $1
#define DBASE  $2
#define DBOUND $3
#define CALG	$17
#endif

#endif /* _IDTCPU_H__ */