prev_cmp_m2_0610.map.qmsg

在ALTERA公司的EPM570上实现的电机脉冲算法

{ "Warning" "WGDFX_INPUTC_OUTPUTC_NOT_SUPPORTED" "WD_SIG " "Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin \"WD_SIG\"" {  } { { "WATCH_DOG.bdf" "" { Schematic "E:/珠海/cpld/WATCH_DOG.bdf" { { 272 616 792 288 "WD_SIG" "" } } } }  } 0 0 "INPUTC, OUTPUTC and BIDIRC pins not supported for pin \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "COUNTER8_AC.vhd 2 1 " "Warning: Using design file COUNTER8_AC.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter8_ac-SYN " "Info: Found design unit 1: counter8_ac-SYN" {  } { { "COUNTER8_AC.vhd" "" { Text "E:/珠海/cpld/COUNTER8_AC.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 COUNTER8_AC " "Info: Found entity 1: COUNTER8_AC" {  } { { "COUNTER8_AC.vhd" "" { Text "E:/珠海/cpld/COUNTER8_AC.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "COUNTER8_AC WATCH_DOG:inst35\|COUNTER8_AC:inst " "Info: Elaborating entity \"COUNTER8_AC\" for hierarchy \"WATCH_DOG:inst35\|COUNTER8_AC:inst\"" {  } { { "WATCH_DOG.bdf" "inst" { Schematic "E:/珠海/cpld/WATCH_DOG.bdf" { { 232 272 416 344 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter WATCH_DOG:inst35\|COUNTER8_AC:inst\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"WATCH_DOG:inst35\|COUNTER8_AC:inst\|lpm_counter:lpm_counter_component\"" {  } { { "COUNTER8_AC.vhd" "lpm_counter_component" { Text "E:/珠海/cpld/COUNTER8_AC.vhd" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "WATCH_DOG:inst35\|COUNTER8_AC:inst\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"WATCH_DOG:inst35\|COUNTER8_AC:inst\|lpm_counter:lpm_counter_component\"" {  } { { "COUNTER8_AC.vhd" "" { Text "E:/珠海/cpld/COUNTER8_AC.vhd" 76 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_i4i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_i4i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_i4i " "Info: Found entity 1: cntr_i4i" {  } { { "db/cntr_i4i.tdf" "" { Text "E:/珠海/cpld/db/cntr_i4i.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_i4i WATCH_DOG:inst35\|COUNTER8_AC:inst\|lpm_counter:lpm_counter_component\|cntr_i4i:auto_generated " "Info: Elaborating entity \"cntr_i4i\" for hierarchy \"WATCH_DOG:inst35\|COUNTER8_AC:inst\|lpm_counter:lpm_counter_component\|cntr_i4i:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "LPM_BUSTRI_UDIR_8.vhd 2 1 " "Warning: Using design file LPM_BUSTRI_UDIR_8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_bustri_udir_8-SYN " "Info: Found design unit 1: lpm_bustri_udir_8-SYN" {  } { { "LPM_BUSTRI_UDIR_8.vhd" "" { Text "E:/珠海/cpld/LPM_BUSTRI_UDIR_8.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 LPM_BUSTRI_UDIR_8 " "Info: Found entity 1: LPM_BUSTRI_UDIR_8" {  } { { "LPM_BUSTRI_UDIR_8.vhd" "" { Text "E:/珠海/cpld/LPM_BUSTRI_UDIR_8.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_BUSTRI_UDIR_8 LPM_BUSTRI_UDIR_8:inst60 " "Info: Elaborating entity \"LPM_BUSTRI_UDIR_8\" for hierarchy \"LPM_BUSTRI_UDIR_8:inst60\"" {  } { { "ZHUHAI.bdf" "inst60" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 824 1304 1440 864 "inst60" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "BUSTRI_UDIR_1.vhd 2 1 " "Warning: Using design file BUSTRI_UDIR_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bustri_udir_1-SYN " "Info: Found design unit 1: bustri_udir_1-SYN" {  } { { "BUSTRI_UDIR_1.vhd" "" { Text "E:/珠海/cpld/BUSTRI_UDIR_1.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 BUSTRI_UDIR_1 " "Info: Found entity 1: BUSTRI_UDIR_1" {  } { { "BUSTRI_UDIR_1.vhd" "" { Text "E:/珠海/cpld/BUSTRI_UDIR_1.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BUSTRI_UDIR_1 BUSTRI_UDIR_1:inst11 " "Info: Elaborating entity \"BUSTRI_UDIR_1\" for hierarchy \"BUSTRI_UDIR_1:inst11\"" {  } { { "ZHUHAI.bdf" "inst11" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 1088 2544 2648 1128 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_bustri BUSTRI_UDIR_1:inst11\|lpm_bustri:lpm_bustri_component " "Info: Elaborating entity \"lpm_bustri\" for hierarchy \"BUSTRI_UDIR_1:inst11\|lpm_bustri:lpm_bustri_component\"" {  } { { "BUSTRI_UDIR_1.vhd" "lpm_bustri_component" { Text "E:/珠海/cpld/BUSTRI_UDIR_1.vhd" 75 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BUSTRI_UDIR_1:inst11\|lpm_bustri:lpm_bustri_component " "Info: Elaborated megafunction instantiation \"BUSTRI_UDIR_1:inst11\|lpm_bustri:lpm_bustri_component\"" {  } { { "BUSTRI_UDIR_1.vhd" "" { Text "E:/珠海/cpld/BUSTRI_UDIR_1.vhd" 75 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "LPM_SHIFTREG_16.vhd 2 1 " "Warning: Using design file LPM_SHIFTREG_16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_shiftreg_16-SYN " "Info: Found design unit 1: lpm_shiftreg_16-SYN" {  } { { "LPM_SHIFTREG_16.vhd" "" { Text "E:/珠海/cpld/LPM_SHIFTREG_16.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 LPM_SHIFTREG_16 " "Info: Found entity 1: LPM_SHIFTREG_16" {  } { { "LPM_SHIFTREG_16.vhd" "" { Text "E:/珠海/cpld/LPM_SHIFTREG_16.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_SHIFTREG_16 LPM_SHIFTREG_16:inst28 " "Info: Elaborating entity \"LPM_SHIFTREG_16\" for hierarchy \"LPM_SHIFTREG_16:inst28\"" {  } { { "ZHUHAI.bdf" "inst28" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { -168 2448 2592 -88 "inst28" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_shiftreg LPM_SHIFTREG_16:inst28\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborating entity \"lpm_shiftreg\" for hierarchy \"LPM_SHIFTREG_16:inst28\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "LPM_SHIFTREG_16.vhd" "lpm_shiftreg_component" { Text "E:/珠海/cpld/LPM_SHIFTREG_16.vhd" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "LPM_SHIFTREG_16:inst28\|lpm_shiftreg:lpm_shiftreg_component " "Info: Elaborated megafunction instantiation \"LPM_SHIFTREG_16:inst28\|lpm_shiftreg:lpm_shiftreg_component\"" {  } { { "LPM_SHIFTREG_16.vhd" "" { Text "E:/珠海/cpld/LPM_SHIFTREG_16.vhd" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[7\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[7\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[6\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[6\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[5\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[5\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[4\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[4\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[3\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[3\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[2\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[2\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[1\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[1\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[0\] " "Warning: Converting TRI node \"BUSTRI_BDIR_8:inst29\|lpm_bustri:lpm_bustri_component\|din\[0\]\" that feeds logic to a wire" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 46 6 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "QEP_CNT:inst9\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\] QEP_CNT:inst9\|LPM_FD1:inst10\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Duplicate register \"QEP_CNT:inst9\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\]\" merged to single register \"QEP_CNT:inst9\|LPM_FD1:inst10\|lpm_ff:lpm_ff_component\|dffs\[0\]\", power-up level changed" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "QEP_CNT:inst9\|LPM_FD1:inst24\|lpm_ff:lpm_ff_component\|dffs\[0\] QEP_CNT:inst9\|LPM_FD1:inst10\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Duplicate register \"QEP_CNT:inst9\|LPM_FD1:inst24\|lpm_ff:lpm_ff_component\|dffs\[0\]\" merged to single register \"QEP_CNT:inst9\|LPM_FD1:inst10\|lpm_ff:lpm_ff_component\|dffs\[0\]\", power-up level changed" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "QEP_CNT:inst9\|LPM_FD1:inst30\|lpm_ff:lpm_ff_component\|dffs\[0\] QEP_CNT:inst9\|LPM_FD1:inst10\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Duplicate register \"QEP_CNT:inst9\|LPM_FD1:inst30\|lpm_ff:lpm_ff_component\|dffs\[0\]\" merged to single register \"QEP_CNT:inst9\|LPM_FD1:inst10\|lpm_ff:lpm_ff_component\|dffs\[0\]\"" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "QEP_CNT:inst9\|LPM_FD1:inst4\|lpm_ff:lpm_ff_component\|dffs\[0\] QEP_CNT:inst9\|LPM_FD1:inst13\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Duplicate register \"QEP_CNT:inst9\|LPM_FD1:inst4\|lpm_ff:lpm_ff_component\|dffs\[0\]\" merged to single register \"QEP_CNT:inst9\|LPM_FD1:inst13\|lpm_ff:lpm_ff_component\|dffs\[0\]\", power-up level changed" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "QEP_CNT:inst9\|LPM_FD1:inst27\|lpm_ff:lpm_ff_component\|dffs\[0\] QEP_CNT:inst9\|LPM_FD1:inst13\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Duplicate register \"QEP_CNT:inst9\|LPM_FD1:inst27\|lpm_ff:lpm_ff_component\|dffs\[0\]\" merged to single register \"QEP_CNT:inst9\|LPM_FD1:inst13\|lpm_ff:lpm_ff_component\|dffs\[0\]\", power-up level changed" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "QEP_CNT:inst9\|LPM_FD1:inst8\|lpm_ff:lpm_ff_component\|dffs\[0\] QEP_CNT:inst9\|LPM_FD1:inst13\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Duplicate register \"QEP_CNT:inst9\|LPM_FD1:inst8\|lpm_ff:lpm_ff_component\|dffs\[0\]\" merged to single register \"QEP_CNT:inst9\|LPM_FD1:inst13\|lpm_ff:lpm_ff_component\|dffs\[0\]\"" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 4 " "Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst37/lpm_counter_component/auto_generated/safe_q\[12\] " "Info: Register \"inst37/lpm_counter_component/auto_generated/safe_q\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst37/lpm_counter_component/auto_generated/safe_q\[13\] " "Info: Register \"inst37/lpm_counter_component/auto_generated/safe_q\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst37/lpm_counter_component/auto_generated/safe_q\[14\] " "Info: Register \"inst37/lpm_counter_component/auto_generated/safe_q\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst37/lpm_counter_component/auto_generated/safe_q\[15\] " "Info: Register \"inst37/lpm_counter_component/auto_generated/safe_q\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "313 " "Info: Implemented 313 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Info: Implemented 26 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "9 " "Info: Implemented 9 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "263 " "Info: Implemented 263 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 37 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "157 " "Info: Allocated 157 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 16 22:35:58 2007 " "Info: Processing ended: Tue Oct 16 22:35:58 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}