m2_0610.fit.qmsg

在ALTERA公司的EPM570上实现的电机脉冲算法

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.168 ns register pin " "Info: Estimated most critical path is register to pin delay of 9.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LPM_FD16:inst40\|lpm_ff:lpm_ff_component\|dffs\[7\] 1 REG LAB_X3_Y1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y1; Fanout = 1; REG Node = 'LPM_FD16:inst40\|lpm_ff:lpm_ff_component\|dffs\[7\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LPM_FD16:inst40|lpm_ff:lpm_ff_component|dffs[7] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.200 ns) 1.432 ns LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1417 2 COMB LAB_X3_Y1 1 " "Info: 2: + IC(1.232 ns) + CELL(0.200 ns) = 1.432 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1417'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.432 ns" { LPM_FD16:inst40|lpm_ff:lpm_ff_component|dffs[7] LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1417 } "NODE_NAME" } } { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 43 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 2.612 ns LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1414 3 COMB LAB_X3_Y1 1 " "Info: 3: + IC(0.266 ns) + CELL(0.914 ns) = 2.612 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1414'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1417 LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1414 } "NODE_NAME" } } { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 43 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.914 ns) 3.792 ns LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1468 4 COMB LAB_X3_Y1 1 " "Info: 4: + IC(0.266 ns) + CELL(0.914 ns) = 3.792 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1468'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1414 LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1468 } "NODE_NAME" } } { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 43 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.914 ns) 5.048 ns LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1427 5 COMB LAB_X3_Y1 1 " "Info: 5: + IC(0.342 ns) + CELL(0.914 ns) = 5.048 ns; Loc. = LAB_X3_Y1; Fanout = 1; COMB Node = 'LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1427'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1468 LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1427 } "NODE_NAME" } } { "lpm_bustri.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_bustri.tdf" 43 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.798 ns) + CELL(2.322 ns) 9.168 ns D\[7\] 6 PIN PIN_100 0 " "Info: 6: + IC(1.798 ns) + CELL(2.322 ns) = 9.168 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'D\[7\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.120 ns" { LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1427 D[7] } "NODE_NAME" } } { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.264 ns ( 57.42 % ) " "Info: Total cell delay = 5.264 ns ( 57.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.904 ns ( 42.58 % ) " "Info: Total interconnect delay = 3.904 ns ( 42.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.168 ns" { LPM_FD16:inst40|lpm_ff:lpm_ff_component|dffs[7] LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1417 LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1414 LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1468 LPM_BUSTRI_UDIR_8:inst77|lpm_bustri:lpm_bustri_component|dout[7]~1427 D[7] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_VERY_HIGH_HOLD_REQUIREMENTS_DETECTED" "2 561 " "Warning: 2 (of 561) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." { { "Info" "IFITAPI_FITAPI_INFO_VPR_REGISTERS_WITH_VERY_HIGH_HOLD_REQUIREMENTS" "2 " "Info: Found 2 Registers with very high hold time requirements" { { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Node \"PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Registered output is \"PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\]\"" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PULSE_GEN:inst20|LPM_FD1:inst16|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PULSE_GEN:inst20|LPM_FD1:inst16|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } }  } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "PULSE_GEN:inst20\|COUNTER16_L_E:inst7\|lpm_counter:lpm_counter_component\|cntr_obj:auto_generated\|cout " "Info: Combinational output is \"PULSE_GEN:inst20\|COUNTER16_L_E:inst7\|lpm_counter:lpm_counter_component\|cntr_obj:auto_generated\|cout\"" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PULSE_GEN:inst20|LPM_FD1:inst16|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PULSE_GEN:inst20|LPM_FD1:inst16|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } }  } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0}  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "PULSE_GEN:inst20\|LPM_FD1:inst16\|lpm_ff:lpm_ff_component\|dffs\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PULSE_GEN:inst20|LPM_FD1:inst16|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { PULSE_GEN:inst20|LPM_FD1:inst16|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "Filter:inst61\|LPM_FD1:inst2\|lpm_ff:lpm_ff_component\|dffs\[0\] " "Info: Node \"Filter:inst61\|LPM_FD1:inst2\|lpm_ff:lpm_ff_component\|dffs\[0\]\"" {  } { { "lpm_ff.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Filter:inst61\|LPM_FD1:inst2\|lpm_ff:lpm_ff_component\|dffs\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Filter:inst61|LPM_FD1:inst2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { Filter:inst61|LPM_FD1:inst2|lpm_ff:lpm_ff_component|dffs[0] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found %1!d! Registers with very high hold time requirements" 0 0 "" 0}  } {  } 0 0 "%1!d! (of %2!d!) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 32 " "Info: Average interconnect usage is 32% of the available device resources. Peak interconnect usage is 32%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X0_Y0 X8_Y5 " "Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1467 " "Info: Following pins have the same output enable: LPM_BUSTRI_UDIR_8:inst77\|lpm_bustri:lpm_bustri_component\|dout\[7\]~1467" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[7\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[3\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[6\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[4\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[2\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[0\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[5\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin D\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 448 -152 24 464 "D\[7..0\]" "" } { 440 24 60 456 "D\[7..0\]" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "D\[1\]" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "LPM_FD8:inst2\|lpm_ff:lpm_ff_component\|dffs\[5\] " "Info: Following pins have the same output enable: LPM_FD8:inst2\|lpm_ff:lpm_ff_component\|dffs\[5\]" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SDA 3.3-V LVTTL " "Info: Type bidirectional pin SDA uses the 3.3-V LVTTL I/O standard" {  } { { "ZHUHAI.bdf" "" { Schematic "E:/珠海/cpld/ZHUHAI.bdf" { { 1104 2704 2880 1120 "SDA" "" } } } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "SDA" } } } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDA } "NODE_NAME" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDA } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/珠海/cpld/M2_0610.fit.smsg " "Info: Generated suppressed messages file E:/珠海/cpld/M2_0610.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 16 22:38:13 2007 " "Info: Processing ended: Tue Oct 16 22:38:13 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}