m2_0610.hier_info

在ALTERA公司的EPM570上实现的电机脉冲算法

|ZHUHAI
XINT2 <= Filter:inst61.SIG_OUT
CLKIN => COUNTER16:inst37.clock
CLKIN => PULSE_GEN:inst20.CLK
QZ1 => Filter:inst61.SIG_IN
Test1 <= PULSE_1.DB_MAX_OUTPUT_PORT_TYPE
QF1 => QEP_CNT:inst9.QEPA
QF2 => QEP_CNT:inst9.QEPB
CO1 <= CTRL_SIG0[1].DB_MAX_OUTPUT_PORT_TYPE
WR => LPM_OR2:inst14.data0
WR => LPM_OR2:inst22.data0
WR => LPM_OR2:inst16.data0
WR => LPM_OR2:inst19.data0
WR => lpm_or2:inst58.data0
WR => LPM_OR2:inst23.data0
A14 => inst75.IN0
A15 => inst75.IN1
A0 => inst21.PADIO
A1 => inst32.PADIO
A2 => inst50.PADIO
A3 => inst51.PADIO
RD => LPM_INV1:inst43.data
RD => LPM_INV1:inst63.data
RD => LPM_INV1:inst44.data
RD => LPM_INV1:inst72.data
RD => LPM_INV1:inst17.data
RD => LPM_INV1:inst73.data
RD => LPM_INV1:inst4.data
RD => LPM_INV1:inst80.data
RD => LPM_INV1:inst86.data
LMT_A => LPM_BUSTRI_UDIR_8:inst60.data[0]
LMT_B => LPM_BUSTRI_UDIR_8:inst60.data[1]
HM1 => LPM_BUSTRI_UDIR_8:inst60.data[2]
SERDY1 => LPM_BUSTRI_UDIR_8:inst60.data[3]
CIN1 => LPM_BUSTRI_UDIR_8:inst8.data[0]
CIN2 => LPM_BUSTRI_UDIR_8:inst8.data[1]
CIN3 => LPM_BUSTRI_UDIR_8:inst8.data[2]
CIN4 => LPM_BUSTRI_UDIR_8:inst8.data[3]
CIN5 => LPM_BUSTRI_UDIR_8:inst8.data[4]
CIN6 => LPM_BUSTRI_UDIR_8:inst8.data[5]
SIN => LPM_BUSTRI_UDIR_8:inst8.data[6]
XIN => LPM_BUSTRI_UDIR_8:inst8.data[7]
SDA <= BUSTRI_UDIR_1:inst11.tridata[0]
ADC_CLK => inst18.PADIO
ADC_DATA => inst25.PADIO
D[0] <= BUSTRI_BDIR_8:inst29.tridata[0]
D[1] <= BUSTRI_BDIR_8:inst29.tridata[1]
D[2] <= BUSTRI_BDIR_8:inst29.tridata[2]
D[3] <= BUSTRI_BDIR_8:inst29.tridata[3]
D[4] <= BUSTRI_BDIR_8:inst29.tridata[4]
D[5] <= BUSTRI_BDIR_8:inst29.tridata[5]
D[6] <= BUSTRI_BDIR_8:inst29.tridata[6]
D[7] <= BUSTRI_BDIR_8:inst29.tridata[7]
CO2 <= CTRL_SIG0[2].DB_MAX_OUTPUT_PORT_TYPE
CO3 <= CTRL_SIG0[3].DB_MAX_OUTPUT_PORT_TYPE
CO4 <= CTRL_SIG0[4].DB_MAX_OUTPUT_PORT_TYPE
CO5 <= CTRL_SIG0[5].DB_MAX_OUTPUT_PORT_TYPE
CO6 <= CTRL_SIG0[6].DB_MAX_OUTPUT_PORT_TYPE
SON2 <= LPM_INV1:inst45.result
AL_CL2 <= CTRL_SIG1[3].DB_MAX_OUTPUT_PORT_TYPE
F2 <= CTRL_SIG1[1].DB_MAX_OUTPUT_PORT_TYPE
PUL <= PULSE1_OUT.DB_MAX_OUTPUT_PORT_TYPE
TDRIB <= CTRL_SIG0[0].DB_MAX_OUTPUT_PORT_TYPE
KIN <= inst24.PADIO
SCL <= CTRL_SIG3[6].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61
SIG_OUT <= LPM_OR3:inst6.result
SIG_IN => LPM_FD1:inst.data
FCK => LPM_FD1:inst.clock
FCK => LPM_FD1:inst2.clock
FCK => LPM_FD1:inst1.clock


|ZHUHAI|Filter:inst61|LPM_OR3:inst6
data0 => LPM_OR:lpm_or_component.DATA[0][0]
data1 => LPM_OR:lpm_or_component.DATA[1][0]
data2 => LPM_OR:lpm_or_component.DATA[2][0]
result <= LPM_OR:lpm_or_component.RESULT[0]


|ZHUHAI|Filter:inst61|LPM_OR3:inst6|LPM_OR:lpm_or_component
data[0][0] => or_node[0][1].IN1
data[1][0] => or_node[0][1].IN0
data[2][0] => or_node[0][2].IN0
result[0] <= or_node[0][2].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61|LPM_AND2:inst3
data0 => LPM_AND:lpm_and_component.DATA[0][0]
data1 => LPM_AND:lpm_and_component.DATA[1][0]
result <= LPM_AND:lpm_and_component.RESULT[0]


|ZHUHAI|Filter:inst61|LPM_AND2:inst3|LPM_AND:lpm_and_component
data[0][0] => and_node[0][1].IN1
data[1][0] => and_node[0][1].IN0
result[0] <= and_node[0][1].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61|LPM_FD1:inst
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|Filter:inst61|LPM_FD1:inst|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61|LPM_FD1:inst2
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|Filter:inst61|LPM_FD1:inst2|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61|LPM_AND2:inst4
data0 => LPM_AND:lpm_and_component.DATA[0][0]
data1 => LPM_AND:lpm_and_component.DATA[1][0]
result <= LPM_AND:lpm_and_component.RESULT[0]


|ZHUHAI|Filter:inst61|LPM_AND2:inst4|LPM_AND:lpm_and_component
data[0][0] => and_node[0][1].IN1
data[1][0] => and_node[0][1].IN0
result[0] <= and_node[0][1].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61|LPM_FD1:inst1
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|Filter:inst61|LPM_FD1:inst1|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|Filter:inst61|LPM_AND2:inst5
data0 => LPM_AND:lpm_and_component.DATA[0][0]
data1 => LPM_AND:lpm_and_component.DATA[1][0]
result <= LPM_AND:lpm_and_component.RESULT[0]


|ZHUHAI|Filter:inst61|LPM_AND2:inst5|LPM_AND:lpm_and_component
data[0][0] => and_node[0][1].IN1
data[1][0] => and_node[0][1].IN0
result[0] <= and_node[0][1].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|COUNTER16:inst37
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]
q[12] <= lpm_counter:lpm_counter_component.q[12]
q[13] <= lpm_counter:lpm_counter_component.q[13]
q[14] <= lpm_counter:lpm_counter_component.q[14]
q[15] <= lpm_counter:lpm_counter_component.q[15]


|ZHUHAI|COUNTER16:inst37|lpm_counter:lpm_counter_component
clock => cntr_49h:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_49h:auto_generated.q[0]
q[1] <= cntr_49h:auto_generated.q[1]
q[2] <= cntr_49h:auto_generated.q[2]
q[3] <= cntr_49h:auto_generated.q[3]
q[4] <= cntr_49h:auto_generated.q[4]
q[5] <= cntr_49h:auto_generated.q[5]
q[6] <= cntr_49h:auto_generated.q[6]
q[7] <= cntr_49h:auto_generated.q[7]
q[8] <= cntr_49h:auto_generated.q[8]
q[9] <= cntr_49h:auto_generated.q[9]
q[10] <= cntr_49h:auto_generated.q[10]
q[11] <= cntr_49h:auto_generated.q[11]
q[12] <= cntr_49h:auto_generated.q[12]
q[13] <= cntr_49h:auto_generated.q[13]
q[14] <= cntr_49h:auto_generated.q[14]
q[15] <= cntr_49h:auto_generated.q[15]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|ZHUHAI|COUNTER16:inst37|lpm_counter:lpm_counter_component|cntr_49h:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT


|ZHUHAI|QEP_CNT:inst9
QEPA_F <= Filter:inst61.SIG_OUT
CLK => LPM_FD1:inst.clock
CLK => LPM_FD1:inst33.clock
QEPA => Filter:inst61.SIG_IN
QEPB_F <= Filter:inst62.SIG_OUT
QEPB => Filter:inst62.SIG_IN
PULSE <= LPM_FD1:inst33.q
CNT_UP <= LPM_FDCPE:inst34.q


|ZHUHAI|QEP_CNT:inst9|Filter:inst61
SIG_OUT <= LPM_OR3:inst6.result
SIG_IN => LPM_FD1:inst.data
FCK => LPM_FD1:inst.clock
FCK => LPM_FD1:inst2.clock
FCK => LPM_FD1:inst1.clock


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_OR3:inst6
data0 => LPM_OR:lpm_or_component.DATA[0][0]
data1 => LPM_OR:lpm_or_component.DATA[1][0]
data2 => LPM_OR:lpm_or_component.DATA[2][0]
result <= LPM_OR:lpm_or_component.RESULT[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_OR3:inst6|LPM_OR:lpm_or_component
data[0][0] => or_node[0][1].IN1
data[1][0] => or_node[0][1].IN0
data[2][0] => or_node[0][2].IN0
result[0] <= or_node[0][2].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_AND2:inst3
data0 => LPM_AND:lpm_and_component.DATA[0][0]
data1 => LPM_AND:lpm_and_component.DATA[1][0]
result <= LPM_AND:lpm_and_component.RESULT[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_AND2:inst3|LPM_AND:lpm_and_component
data[0][0] => and_node[0][1].IN1
data[1][0] => and_node[0][1].IN0
result[0] <= and_node[0][1].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_FD1:inst
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_FD1:inst|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_FD1:inst2
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_FD1:inst2|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_AND2:inst4
data0 => LPM_AND:lpm_and_component.DATA[0][0]
data1 => LPM_AND:lpm_and_component.DATA[1][0]
result <= LPM_AND:lpm_and_component.RESULT[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_AND2:inst4|LPM_AND:lpm_and_component
data[0][0] => and_node[0][1].IN1
data[1][0] => and_node[0][1].IN0
result[0] <= and_node[0][1].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_FD1:inst1
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_FD1:inst1|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sload => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_AND2:inst5
data0 => LPM_AND:lpm_and_component.DATA[0][0]
data1 => LPM_AND:lpm_and_component.DATA[1][0]
result <= LPM_AND:lpm_and_component.RESULT[0]


|ZHUHAI|QEP_CNT:inst9|Filter:inst61|LPM_AND2:inst5|LPM_AND:lpm_and_component
data[0][0] => and_node[0][1].IN1
data[1][0] => and_node[0][1].IN0
result[0] <= and_node[0][1].DB_MAX_OUTPUT_PORT_TYPE


|ZHUHAI|QEP_CNT:inst9|LPM_FD1:inst
clock => lpm_ff:lpm_ff_component.clock
data => lpm_ff:lpm_ff_component.data[0]
q <= lpm_ff:lpm_ff_component.q[0]


|ZHUHAI|QEP_CNT:inst9|LPM_FD1:inst|lpm_ff:lpm_ff_component
data[0] => dffs[0].DATAIN
clock => dffs[0].CLK
enable => dffs[0].ENA
aclr => ~NO_FANOUT~