m2_0610.vho

在ALTERA公司的EPM570上实现的电机脉冲算法

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

-- DATE "10/16/2007 22:38:31"

-- 
-- Device: Altera EPM240T100C5 Package TQFP100
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	ZHUHAI IS
    PORT (
	XINT2 : OUT std_logic;
	CLKIN : IN std_logic;
	QZ1 : IN std_logic;
	Test1 : OUT std_logic;
	QF1 : IN std_logic;
	QF2 : IN std_logic;
	CO1 : OUT std_logic;
	WR : IN std_logic;
	A14 : IN std_logic;
	A15 : IN std_logic;
	A0 : IN std_logic;
	A1 : IN std_logic;
	A2 : IN std_logic;
	A3 : IN std_logic;
	RD : IN std_logic;
	LMT_A : IN std_logic;
	LMT_B : IN std_logic;
	HM1 : IN std_logic;
	SERDY1 : IN std_logic;
	CIN1 : IN std_logic;
	CIN2 : IN std_logic;
	CIN3 : IN std_logic;
	CIN4 : IN std_logic;
	CIN5 : IN std_logic;
	CIN6 : IN std_logic;
	SIN : IN std_logic;
	XIN : IN std_logic;
	SDA : INOUT std_logic;
	ADC_CLK : IN std_logic;
	ADC_DATA : IN std_logic;
	D : INOUT std_logic_vector(7 DOWNTO 0);
	CO2 : OUT std_logic;
	CO3 : OUT std_logic;
	CO4 : OUT std_logic;
	CO5 : OUT std_logic;
	CO6 : OUT std_logic;
	SON2 : OUT std_logic;
	AL_CL2 : OUT std_logic;
	F2 : OUT std_logic;
	PUL : OUT std_logic;
	TDRIB : OUT std_logic;
	KIN : OUT std_logic;
	SCL : OUT std_logic
	);
END ZHUHAI;

ARCHITECTURE structure OF ZHUHAI IS
SIGNAL GNDs : std_logic_vector(2048 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(2048 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL ww_XINT2 : std_logic;
SIGNAL ww_CLKIN : std_logic;
SIGNAL ww_QZ1 : std_logic;
SIGNAL ww_Test1 : std_logic;
SIGNAL ww_QF1 : std_logic;
SIGNAL ww_QF2 : std_logic;
SIGNAL ww_CO1 : std_logic;
SIGNAL ww_WR : std_logic;
SIGNAL ww_A14 : std_logic;
SIGNAL ww_A15 : std_logic;
SIGNAL ww_A0 : std_logic;
SIGNAL ww_A1 : std_logic;
SIGNAL ww_A2 : std_logic;
SIGNAL ww_A3 : std_logic;
SIGNAL ww_RD : std_logic;
SIGNAL ww_LMT_A : std_logic;
SIGNAL ww_LMT_B : std_logic;
SIGNAL ww_HM1 : std_logic;
SIGNAL ww_SERDY1 : std_logic;
SIGNAL ww_CIN1 : std_logic;
SIGNAL ww_CIN2 : std_logic;
SIGNAL ww_CIN3 : std_logic;
SIGNAL ww_CIN4 : std_logic;
SIGNAL ww_CIN5 : std_logic;
SIGNAL ww_CIN6 : std_logic;
SIGNAL ww_SIN : std_logic;
SIGNAL ww_XIN : std_logic;
SIGNAL ww_ADC_CLK : std_logic;
SIGNAL ww_ADC_DATA : std_logic;
SIGNAL ww_CO2 : std_logic;
SIGNAL ww_CO3 : std_logic;
SIGNAL ww_CO4 : std_logic;
SIGNAL ww_CO5 : std_logic;
SIGNAL ww_CO6 : std_logic;
SIGNAL ww_SON2 : std_logic;
SIGNAL ww_AL_CL2 : std_logic;
SIGNAL ww_F2 : std_logic;
SIGNAL ww_PUL : std_logic;
SIGNAL ww_TDRIB : std_logic;
SIGNAL ww_KIN : std_logic;
SIGNAL ww_SCL : std_logic;
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella5_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella5_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \CLKIN~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \inst9|inst|lpm_ff_component|dffs[0]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst9|inst|lpm_ff_component|dffs[0]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|cout_bit_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|cout_bit_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst16|lpm_ff_component|dffs[0]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst16|lpm_ff_component|dffs[0]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella7_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella7_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst7|lpm_counter_component|auto_generated|counter_cella15_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst7|lpm_counter_component|auto_generated|counter_cella15_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella10_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella10_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella6_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella6_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst17|lpm_ff_component|dffs[15]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst17|lpm_ff_component|dffs[15]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst|lpm_ff_component|dffs[0]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst|lpm_ff_component|dffs[0]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst39|lpm_ff_component|dffs[0]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst39|lpm_ff_component|dffs[0]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst7|lpm_counter_component|auto_generated|counter_cella14_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst7|lpm_counter_component|auto_generated|counter_cella14_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst|lpm_decode_component|auto_generated|w_anode69w[3]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst|lpm_decode_component|auto_generated|w_anode69w[3]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella9_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella9_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella5_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella5_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst13|lpm_ff_component|dffs[7]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst13|lpm_ff_component|dffs[7]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst18|lpm_ff_component|dffs[0]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst18|lpm_ff_component|dffs[0]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst17|lpm_ff_component|dffs[14]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst17|lpm_ff_component|dffs[14]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst7|lpm_counter_component|auto_generated|counter_cella13_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst7|lpm_counter_component|auto_generated|counter_cella13_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella8_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst37|lpm_counter_component|auto_generated|counter_cella8_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella4_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst35|inst|lpm_counter_component|auto_generated|counter_cella4_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst13|lpm_ff_component|dffs[6]_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \inst20|inst13|lpm_ff_component|dffs[6]_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inst20|inst17|lpm_ff_component|dffs[13]_modesel\ : std_logic_vector(12 DOWNTO 0);