m2_0610_pt_vhd.tcl

在ALTERA公司的EPM570上实现的电机脉冲算法

## Copyright (C) 1991-2007 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

## DATE "10/16/2007 22:38:31"

## 
## Device: Altera EPM240T100C5 Package TQFP100
## 

## 
## This Tcl script should be used for PrimeTime (VHDL) only
## 

## This file can be sourced in primetime

set report_default_significant_digits 3
set hierarchy_separator .

set quartus_root "d:/altera/71/quartus/"
set search_path [list . [format "%s%s" $quartus_root "eda/synopsys/primetime/lib"]  ]

set link_path [list *  maxii_io_lib.db maxii_asynch_lcell_lib.db  maxii_ufm_lib.db maxii_lcell_register_lib.db  alt_vtl.db]

read_vhdl  -vhdl_compiler  maxii_all_pt.vhd 

##########################
## DESIGN ENTRY SECTION ##
##########################

read_vhdl  -vhdl_compiler M2_0610.vho
current_design ZHUHAI
link
## Set variable timing_propagate_single_condition_min_slew to false only for versions 2004.06 and earlier
regexp {([1-9][0-9][0-9][0-9]\.[0-9][0-9])} $sh_product_version dummy version
if { [string compare "2004.06" $version ] != -1 } {
   set timing_propagate_single_condition_min_slew false
}
set_operating_conditions -analysis_type single
read_sdf M2_0610_vhd.sdo

################################
## TIMING CONSTRAINTS SECTION ##
################################


## Start clock definition ##
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { CLKIN } ] -name CLKIN  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { WR } ] -name WR  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { A15 } ] -name A15  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { A1 } ] -name A1  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { A3 } ] -name A3  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { A14 } ] -name A14  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { A0 } ] -name A0  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { A2 } ] -name A2  
# WARNING:  The required clock period is not set. The default value (100 ns) is used. 
create_clock -period 100.000 -waveform {0.000 50.000} [get_ports { ADC_CLK } ] -name ADC_CLK  

set_propagated_clock [all_clocks]
set_clock_groups -asynchronous \
-group {CLKIN} \
-group {WR} \
-group {A15} \
-group {A1} \
-group {A3} \
-group {A14} \
-group {A0} \
-group {A2} \
-group {ADC_CLK}
## End clock definition ##

## Start create collections ##
## End create collections ##

## Start global settings ##
## End global settings ##

## Start collection commands definition ##

## End collection commands definition ##

## Start individual pin commands definition ##
## End individual pin commands definition ##

## Start Output pin capacitance definition ##
set_load -pin_load 10 [get_ports { AL_CL2 } ]
set_load -pin_load 10 [get_ports { CO1 } ]
set_load -pin_load 10 [get_ports { CO2 } ]
set_load -pin_load 10 [get_ports { CO3 } ]
set_load -pin_load 10 [get_ports { CO4 } ]
set_load -pin_load 10 [get_ports { CO5 } ]
set_load -pin_load 10 [get_ports { CO6 } ]
set_load -pin_load 10 [get_ports { D[0] } ]
set_load -pin_load 10 [get_ports { D[1] } ]
set_load -pin_load 10 [get_ports { D[2] } ]
set_load -pin_load 10 [get_ports { D[3] } ]
set_load -pin_load 10 [get_ports { D[4] } ]
set_load -pin_load 10 [get_ports { D[5] } ]
set_load -pin_load 10 [get_ports { D[6] } ]
set_load -pin_load 10 [get_ports { D[7] } ]
set_load -pin_load 10 [get_ports { F2 } ]
set_load -pin_load 10 [get_ports { KIN } ]
set_load -pin_load 10 [get_ports { PUL } ]
set_load -pin_load 10 [get_ports { SCL } ]
set_load -pin_load 10 [get_ports { SDA } ]
set_load -pin_load 10 [get_ports { SON2 } ]
set_load -pin_load 10 [get_ports { TDRIB } ]
set_load -pin_load 10 [get_ports { Test1 } ]
set_load -pin_load 10 [get_ports { XINT2 } ]
## End Output pin capacitance definition ##

## Start clock uncertainty definition ##
## End clock uncertainty definition ##

## Start Multicycle and Cut Path definition ##
## End Multicycle and Cut Path definition ##

## Destroy Collections ##

update_timing