m2_0610.fit.rpt

在ALTERA公司的EPM570上实现的电机脉冲算法

; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner             ; On                             ; On                             ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; Slow Slew Rate                                                     ; Off                            ; Off                            ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/珠海/cpld/M2_0610.pin.


+-------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                               ;
+---------------------------------------------+---------------------------------------------------------------+
; Resource                                    ; Usage                                                         ;
+---------------------------------------------+---------------------------------------------------------------+
; Total logic elements                        ; 217 / 240 ( 90 % )                                            ;
;     -- Combinational with no register       ; 36                                                            ;
;     -- Register only                        ; 61                                                            ;
;     -- Combinational with a register        ; 120                                                           ;
;                                             ;                                                               ;
; Logic element usage by number of LUT inputs ;                                                               ;
;     -- 4 input functions                    ; 61                                                            ;
;     -- 3 input functions                    ; 44                                                            ;
;     -- 2 input functions                    ; 39                                                            ;
;     -- 1 input functions                    ; 30                                                            ;
;     -- 0 input functions                    ; 43                                                            ;
;                                             ;                                                               ;
; Logic elements by mode                      ;                                                               ;
;     -- normal mode                          ; 153                                                           ;
;     -- arithmetic mode                      ; 64                                                            ;
;     -- qfbk mode                            ; 44                                                            ;
;     -- register cascade mode                ; 0                                                             ;
;     -- synchronous clear/load mode          ; 100                                                           ;
;     -- asynchronous clear/load mode         ; 11                                                            ;
;                                             ;                                                               ;
; Total registers                             ; 181 / 240 ( 75 % )                                            ;
; Total LABs                                  ; 24 / 24 ( 100 % )                                             ;
; Logic elements in carry chains              ; 69                                                            ;
; User inserted logic elements                ; 0                                                             ;
; Virtual pins                                ; 0                                                             ;
; I/O pins                                    ; 50 / 80 ( 63 % )                                              ;
;     -- Clock pins                           ; 2                                                             ;
; Global signals                              ; 4                                                             ;
; UFM blocks                                  ; 0 / 1 ( 0 % )                                                 ;
; Global clocks                               ; 4 / 4 ( 100 % )                                               ;
; Average interconnect usage                  ; 32%                                                           ;
; Peak interconnect usage                     ; 32%                                                           ;
; Maximum fan-out node                        ; PULSE_GEN:inst20|LPM_FD1:inst|lpm_ff:lpm_ff_component|dffs[0] ;
; Maximum fan-out                             ; 33                                                            ;
; Highest non-global fan-out signal           ; LPM_OR2:inst19|lpm_or:lpm_or_component|or_node[0][1]          ;
; Highest non-global fan-out                  ; 18                                                            ;
; Total fan-out                               ; 832                                                           ;
; Average fan-out                             ; 3.12                                                          ;
+---------------------------------------------+---------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                      ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+