a86_seg_regs.v

来自「使用CPLD仿真8088核,内有源程序和说明」· Verilog 代码 · 共 50 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"

module a86_seg_regs(rst,clk,we,din,sel,cs,ds,ss,es);

input rst;
wire rst;

input clk;

input we;
input [15:0] din;
input [1:0] sel;
    
output [15:0] cs;
output [15:0] ds;
output [15:0] ss;
output [15:0] es;

// latches
reg [15:0] cs; 
reg [15:0] ds; 
reg [15:0] ss; 
reg [15:0] es; 

// Latch writes to seg regs
always @ (posedge clk)
  if (rst) 
  begin
    cs <= 16'hFFFF;
    ds <= 16'h1000;
    ss <= 16'h2000;
    es <= 16'h3000;
  end else
    if (we) begin
      case(sel)
        2'b01: ds <= din; 
        2'b10: ss <= din; 
        2'b11: es <= din; 
        default cs <= din;
      endcase
    end





endmodule