a86_rom8k_verilog.v

使用CPLD仿真8088核,内有源程序和说明

// http://gforge.openchip.org/projects/a86

module a86_rom8k_verilog(clk,addr,data);

input clk;
input [12:0] addr;
output [127:0] data;
wire [127:0] data;

   // synopsys translate_off
      defparam XLXI_1.INIT_A = 36'h000000000;
      defparam XLXI_1.INIT_B = 36'h000000000;
      defparam XLXI_1.SRVAL_A = 36'h000000000;
      defparam XLXI_1.SRVAL_B = 36'h000000000;
      defparam XLXI_1.WRITE_MODE_A = "WRITE_FIRST";
      defparam XLXI_1.WRITE_MODE_B = "WRITE_FIRST";
   // synopsys translate_on


reg [9:0] addra;
reg [9:0] addrb;

always @(addr) 
  addra[9:0] = addr[12:3];

always @(addra) 
  addrb[9:0] = addra + 10'b0000000001;

RAMB16_S18_S18 ROM_0 (
  .ADDRA( addra ), 
  .ADDRB( addrb ), 
  .CLKA(clk), 
  .CLKB(clk), 
  .DIA(16'b0000000000000000), 
  .DIB(16'b0000000000000000),
  .DIPA(2'b00), 
  .DIPB(2'b00), 
  .ENA( 1'b1 ), 
  .ENB( 1'b1 ), 
  .SSRA( 1'b0 ), 
  .SSRB( 1'b0 ), 
  .WEA( 1'b0 ), 
  .WEB( 1'b0 ),
  .DOA( data[15:0] ), 
  .DOB( data[79:64] ), 
  .DOPA( ), 
  .DOPB( )
  );

RAMB16_S18_S18 ROM_1 (
  .ADDRA( addra ), 
  .ADDRB( addrb ), 
  .CLKA(clk), 
  .CLKB(clk), 
  .DIA(16'b0000000000000000), 
  .DIB(16'b0000000000000000),
  .DIPA(2'b00), 
  .DIPB(2'b00), 
  .ENA( 1'b1 ), 
  .ENB( 1'b1 ), 
  .SSRA( 1'b0 ), 
  .SSRB( 1'b0 ), 
  .WEA( 1'b0 ), 
  .WEB( 1'b0 ),
  .DOA( data[31:16] ), 
  .DOB( data[95:80] ), 
  .DOPA( ), 
  .DOPB( )
  );

RAMB16_S18_S18 ROM_2 (
  .ADDRA( addra ), 
  .ADDRB( addrb ), 
  .CLKA(clk), 
  .CLKB(clk), 
  .DIA(16'b0000000000000000), 
  .DIB(16'b0000000000000000),
  .DIPA(2'b00), 
  .DIPB(2'b00), 
  .ENA( 1'b1 ), 
  .ENB( 1'b1 ), 
  .SSRA( 1'b0 ), 
  .SSRB( 1'b0 ), 
  .WEA( 1'b0 ), 
  .WEB( 1'b0 ),
  .DOA( data[47:32] ), 
  .DOB( data[111:96] ), 
  .DOPA( ), 
  .DOPB( )
  );

RAMB16_S18_S18 ROM_3 (
  .ADDRA( addra ), 
  .ADDRB( addrb ), 
  .CLKA(clk), 
  .CLKB(clk), 
  .DIA(16'b0000000000000000), 
  .DIB(16'b0000000000000000),
  .DIPA(2'b00), 
  .DIPB(2'b00), 
  .ENA( 1'b1 ), 
  .ENB( 1'b1 ), 
  .SSRA( 1'b0 ), 
  .SSRB( 1'b0 ), 
  .WEA( 1'b0 ), 
  .WEB( 1'b0 ),
  .DOA( data[63:48] ), 
  .DOB( data[127:112] ), 
  .DOPA( ), 
  .DOPB( )
  );






endmodule