a86_index_regs.v

来自「使用CPLD仿真8088核,内有源程序和说明」· Verilog 代码 · 共 35 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"

module a86_index_regs(rst,clk,we,sel,di,si,din);
    
input rst;
input clk;
input we;
input sel;
input [15:0] din;
output [15:0] si;
output [15:0] di;


// latches
reg [15:0] si; 
reg [15:0] di; 

// Latch writes to seg regs
always @ (posedge clk)
  if (rst) begin
    si <= 16'h4000; 
    di <= 16'h5000; 
  end else
    if (we) begin
      case(sel)
        1'b0: si <= din; 
        default di <= din;
      endcase
    end


endmodule