a86_flags.v

来自「使用CPLD仿真8088核,内有源程序和说明」· Verilog 代码 · 共 44 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"
`include "a86_defines.v"

module a86_flags(
  clk,
  we,
  wmask,
  outmask,
  outval,
  din,
  flags
  );

input clk;
input we;

input [15:0] wmask;
input [15:0] outmask;
input [15:0] outval;
input [15:0] din;
output [15:0] flags;

reg [15:0] flags; 


// latches
reg [15:0] flags_r; 




// Latch writes to sp reg
always @ (posedge clk)
  if (we) flags_r <= din;

always @ (flags_r)
  flags <= flags_r & outmask;



endmodule