a86_offset_sel.v

来自「使用CPLD仿真8088核,内有源程序和说明」· Verilog 代码 · 共 31 行

// http://gforge.openchip.org/projects/a86

`include "timescale.v"

module a86_offset_sel(
  sel,
  ea,
  sp,
  ip,
  offset);
    
input [1:0] sel;
input [15:0] ea;
input [15:0] sp;
input [15:0] ip;
output [15:0] offset;

reg [15:0] offset;

always @ (sel,sp,ip,ea)
  case(sel)
    2'b01: offset = sp;
    2'b10: offset = ip;
    default offset = ea;
  endcase


//always @(sp,ip,ea)  offset = 16'h1234;

endmodule