a86_adsu16_xilinx.v

使用CPLD仿真8088核,内有源程序和说明

// http://gforge.openchip.org/projects/a86

//
// ADD/SUB with carry in/out and Overflow
// Xilinx Macro, Virtex II/Pro
//

`ifdef a86_vendor_xilinx

module a86_ADSU16_XILINX(A, ADD, B, CI, CO, OFL, S);

input [15:0] A;
input ADD;
input [15:0] B;
input CI;
output CO;
output OFL;
output [15:0] S;

wire C0;
wire C1;
wire C10;
wire C11;
wire C12;
wire C13;
wire C14;
wire C14O;
wire C2;
wire C3;
wire C4;
wire C5;
wire C6;
wire C7;
wire C8;
wire C9;
wire I0;
wire I1;
wire I10;
wire I11;
wire I12;
wire I13;
wire I14;
wire I15;
wire I2;
wire I3;
wire I4;
wire I5;
wire I6;
wire I7;
wire I8;
wire I9;
wire SUB0;
wire SUB1;
wire SUB10;
wire SUB11;
wire SUB12;
wire SUB13;
wire SUB14;
wire SUB15;
wire SUB2;
wire SUB3;
wire SUB4;
wire SUB5;
wire SUB6;
wire SUB7;
wire SUB8;
wire SUB9;
wire dummy;

FMAP I_36_275 (.I1(A[0]), .I2(B[0]), .I3(ADD), .I4(dummy), .O(I0));
   // synthesis attribute RLOC of I_36_275 is "X1Y0"
FMAP I_36_272 (.I1(A[1]), .I2(B[1]), .I3(ADD), .I4(dummy), .O(I1));
   // synthesis attribute RLOC of I_36_272 is "X1Y0"
FMAP I_36_279 (.I1(A[2]), .I2(B[2]), .I3(ADD), .I4(dummy), .O(I2));
   // synthesis attribute RLOC of I_36_279 is "X1Y1"
FMAP I_36_283 (.I1(A[3]), .I2(B[3]), .I3(ADD), .I4(dummy), .O(I3));
   // synthesis attribute RLOC of I_36_283 is "X1Y1"
FMAP I_36_287 (.I1(A[4]), .I2(B[4]), .I3(ADD), .I4(dummy), .O(I4));
   // synthesis attribute RLOC of I_36_287 is "X1Y2"
FMAP I_36_291 (.I1(A[5]), .I2(B[5]), .I3(ADD), .I4(dummy), .O(I5));
   // synthesis attribute RLOC of I_36_291 is "X1Y2"
FMAP I_36_295 (.I1(A[6]), .I2(B[6]), .I3(ADD), .I4(dummy), .O(I6));
   // synthesis attribute RLOC of I_36_295 is "X1Y3"
FMAP I_36_299 (.I1(A[7]), .I2(B[7]), .I3(ADD), .I4(dummy), .O(I7));
   // synthesis attribute RLOC of I_36_299 is "X1Y3"
FMAP I_36_16 (.I1(A[8]), .I2(B[8]), .I3(ADD), .I4(dummy), .O(I8));
   // synthesis attribute RLOC of I_36_16 is "X1Y4"
FMAP I_36_17 (.I1(A[9]), .I2(B[9]), .I3(ADD), .I4(dummy), .O(I9));
   // synthesis attribute RLOC of I_36_17 is "X1Y4"
FMAP I_36_18 (.I1(A[10]), .I2(B[10]), .I3(ADD), .I4(dummy), .O(I10));
   // synthesis attribute RLOC of I_36_18 is "X1Y5"
FMAP I_36_19 (.I1(A[11]), .I2(B[11]), .I3(ADD), .I4(dummy), .O(I11));
   // synthesis attribute RLOC of I_36_19 is "X1Y5"
FMAP I_36_20 (.I1(A[12]), .I2(B[12]), .I3(ADD), .I4(dummy), .O(I12));
   // synthesis attribute RLOC of I_36_20 is "X1Y6"
FMAP I_36_21 (.I1(A[13]), .I2(B[13]), .I3(ADD), .I4(dummy), .O(I13));
   // synthesis attribute RLOC of I_36_21 is "X1Y6"
FMAP I_36_23 (.I1(A[15]), .I2(B[15]), .I3(ADD), .I4(dummy), .O(I15));
   // synthesis attribute RLOC of I_36_23 is "X1Y7"
FMAP I_36_22 (.I1(A[14]), .I2(B[14]), .I3(ADD), .I4(dummy), .O(I14));
   // synthesis attribute RLOC of I_36_22 is "X1Y7"
INV I_36_364 (.I(ADD), .O(SUB9));
INV I_36_366 (.I(ADD), .O(SUB11));
INV I_36_367 (.I(ADD), .O(SUB12));
INV I_36_355 (.I(ADD), .O(SUB0));
INV I_36_356 (.I(ADD), .O(SUB1));
INV I_36_357 (.I(ADD), .O(SUB2));
INV I_36_358 (.I(ADD), .O(SUB3));
INV I_36_359 (.I(ADD), .O(SUB4));
INV I_36_360 (.I(ADD), .O(SUB5));
INV I_36_361 (.I(ADD), .O(SUB6));
INV I_36_362 (.I(ADD), .O(SUB7));
INV I_36_365 (.I(ADD), .O(SUB10));
INV I_36_368 (.I(ADD), .O(SUB13));
INV I_36_369 (.I(ADD), .O(SUB14));
INV I_36_370 (.I(ADD), .O(SUB15));
INV I_36_363 (.I(ADD), .O(SUB8));
MUXCY I_36_64 (.CI(C14), .DI(A[15]), .S(I15), .O(CO));
   // synthesis attribute RLOC of I_36_64 is "X1Y7"
MUXCY_D I_36_107 (.CI(C13), .DI(A[14]), .S(I14), .LO(C14), .O(C14O));
   // synthesis attribute RLOC of I_36_107 is "X1Y7"
MUXCY_L I_36_254 (.CI(C0), .DI(A[1]), .S(I1), .LO(C1));
   // synthesis attribute RLOC of I_36_254 is "X1Y0"
MUXCY_L I_36_253 (.CI(C1), .DI(A[2]), .S(I2), .LO(C2));
   // synthesis attribute RLOC of I_36_253 is "X1Y1"
MUXCY_L I_36_249 (.CI(C5), .DI(A[6]), .S(I6), .LO(C6));
   // synthesis attribute RLOC of I_36_249 is "X1Y3"
MUXCY_L I_36_248 (.CI(C6), .DI(A[7]), .S(I7), .LO(C7));
   // synthesis attribute RLOC of I_36_248 is "X1Y3"
MUXCY_L I_36_255 (.CI(CI), .DI(A[0]), .S(I0), .LO(C0));
   // synthesis attribute RLOC of I_36_255 is "X1Y0"
MUXCY_L I_36_110 (.CI(C12), .DI(A[13]), .S(I13), .LO(C13));
   // synthesis attribute RLOC of I_36_110 is "X1Y6"
MUXCY_L I_36_63 (.CI(C11), .DI(A[12]), .S(I12), .LO(C12));
   // synthesis attribute RLOC of I_36_63 is "X1Y6"
MUXCY_L I_36_252 (.CI(C2), .DI(A[3]), .S(I3), .LO(C3));
   // synthesis attribute RLOC of I_36_252 is "X1Y1"
MUXCY_L I_36_251 (.CI(C3), .DI(A[4]), .S(I4), .LO(C4));
   // synthesis attribute RLOC of I_36_251 is "X1Y2"
MUXCY_L I_36_250 (.CI(C4), .DI(A[5]), .S(I5), .LO(C5));
   // synthesis attribute RLOC of I_36_250 is "X1Y2"
MUXCY_L I_36_58 (.CI(C10), .DI(A[11]), .S(I11), .LO(C11));
   // synthesis attribute RLOC of I_36_58 is "X1Y5"
MUXCY_L I_36_62 (.CI(C9), .DI(A[10]), .S(I10), .LO(C10));
   // synthesis attribute RLOC of I_36_62 is "X1Y5"
MUXCY_L I_36_111 (.CI(C7), .DI(A[8]), .S(I8), .LO(C8));
   // synthesis attribute RLOC of I_36_111 is "X1Y4"
MUXCY_L I_36_55 (.CI(C8), .DI(A[9]), .S(I9), .LO(C9));
   // synthesis attribute RLOC of I_36_55 is "X1Y4"
XOR2 I_36_353 (.I0(C14O), .I1(CO), .O(OFL));
XOR3 I_36_50 (.I0(A[8]), .I1(B[8]), .I2(SUB8), .O(I8));
XOR3 I_36_56 (.I0(A[10]), .I1(B[10]), .I2(SUB10), .O(I10));
XOR3 I_36_57 (.I0(A[11]), .I1(B[11]), .I2(SUB11), .O(I11));
XOR3 I_36_59 (.I0(A[14]), .I1(B[14]), .I2(SUB14), .O(I14));
XOR3 I_36_60 (.I0(A[12]), .I1(B[12]), .I2(SUB12), .O(I12));
XOR3 I_36_79 (.I0(A[15]), .I1(B[15]), .I2(SUB15), .O(I15));
XOR3 I_36_100 (.I0(A[9]), .I1(B[9]), .I2(SUB9), .O(I9));
XOR3 I_36_109 (.I0(A[13]), .I1(B[13]), .I2(SUB13), .O(I13));
XOR3 I_36_245 (.I0(A[5]), .I1(B[5]), .I2(SUB5), .O(I5));
XOR3 I_36_243 (.I0(A[1]), .I1(B[1]), .I2(SUB1), .O(I1));
XOR3 I_36_232 (.I0(A[7]), .I1(B[7]), .I2(SUB7), .O(I7));
XOR3 I_36_225 (.I0(A[4]), .I1(B[4]), .I2(SUB4), .O(I4));
XOR3 I_36_224 (.I0(A[6]), .I1(B[6]), .I2(SUB6), .O(I6));
XOR3 I_36_223 (.I0(A[3]), .I1(B[3]), .I2(SUB3), .O(I3));
XOR3 I_36_222 (.I0(A[2]), .I1(B[2]), .I2(SUB2), .O(I2));
XOR3 I_36_220 (.I0(A[0]), .I1(B[0]), .I2(SUB0), .O(I0));
XORCY I_36_73 (.CI(C7), .LI(I8), .O(S[8]));
XORCY I_36_74 (.CI(C8), .LI(I9), .O(S[9]));
XORCY I_36_76 (.CI(C9), .LI(I10), .O(S[10]));
XORCY I_36_75 (.CI(C10), .LI(I11), .O(S[11]));
XORCY I_36_78 (.CI(C11), .LI(I12), .O(S[12]));
XORCY I_36_77 (.CI(C12), .LI(I13), .O(S[13]));
XORCY I_36_81 (.CI(C13), .LI(I14), .O(S[14]));
XORCY I_36_80 (.CI(C14), .LI(I15), .O(S[15]));
XORCY I_36_226 (.CI(CI), .LI(I0), .O(S[0]));
XORCY I_36_227 (.CI(C0), .LI(I1), .O(S[1]));
XORCY I_36_229 (.CI(C1), .LI(I2), .O(S[2]));
XORCY I_36_228 (.CI(C2), .LI(I3), .O(S[3]));
XORCY I_36_231 (.CI(C3), .LI(I4), .O(S[4]));
XORCY I_36_230 (.CI(C4), .LI(I5), .O(S[5]));
XORCY I_36_234 (.CI(C5), .LI(I6), .O(S[6]));
XORCY I_36_233 (.CI(C6), .LI(I7), .O(S[7]));
endmodule

`endif