cpld_dsp.rpt

cpld max7128s控制3路AD7472采样

Project Information                  h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/07/2008 11:43:44

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
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use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

cpld_dsp  EPM7128SQC100-6  37       27       0      82      52          64 %
cpld_ds1  EPM7128SQC100-6  6        16       0      81      90          63 %

TOTAL:                     43       43       0      163     142         63 %

User Pins:                 23       38       0  



Project Information                  h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Primitive 'OE1' is stuck at VCC
Warning: Primitive 'OE2' is stuck at VCC
Warning: Primitive 'LED0' is stuck at GND
Warning: Primitive 'LED1' is stuck at GND
Info: Reserved unused input pin 'AD3_BUSY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'KEY0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'KEY1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'KEY2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'KEY3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'KEY4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'AD2_BUSY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Warning: Node 'EA4' has an input assignment to chip 'cpld_dsp' but is not used as an input on this chip
Warning: Node 'EA3' has an input assignment to chip 'cpld_dsp' but is not used as an input on this chip
Warning: Node 'EA5' has an input assignment to chip 'cpld_dsp' but is not used as an input on this chip
Warning: Node 'ARM_1' has an input assignment to chip 'cpld_dsp' but is not used as an input on this chip
Warning: Node 'ARM_0' has an input assignment to chip 'cpld_dsp' but is not used as an input on this chip


Project Information                  h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'GCLK1' chosen for auto global Clock
INFO: Signal 'GCLK2' chosen for auto global Clock


Project Information                  h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt

** MULTIPLE PIN CONNECTIONS **


For node name 'EA12'
Connect: {cpld_ds1@14,  cpld_dsp@96}

For node name 'EA11'
Connect: {cpld_ds1@43,  cpld_dsp@95}

For node name 'EA10'
Connect: {cpld_ds1@39,  cpld_dsp@94}

For node name 'EA9'
Connect: {cpld_ds1@65,  cpld_dsp@87}

For node name 'EA8'
Connect: {cpld_ds1@98,  cpld_dsp@86}

For node name 'EA7'
Connect: {cpld_ds1@80,  cpld_dsp@85}

For node name 'EA6'
Connect: {cpld_ds1@54,  cpld_dsp@83}

For node name 'EA5'
Connect: {cpld_dsp@80,  cpld_ds1@1}

For node name 'EA4'
Connect: {cpld_dsp@71,  cpld_ds1@3}

For node name 'EA3'
Connect: {cpld_dsp@54,  cpld_ds1@4}

For node name 'EA2'
Connect: {cpld_ds1@56,  cpld_dsp@19}

For node name 'EA1'
Connect: {cpld_ds1@95,  cpld_dsp@18}

For node name 'EA0'
Connect: {cpld_ds1@27,  cpld_dsp@16}

For node name 'GCLK1'
Connect: {cpld_ds1@89,  cpld_dsp@89}

For node name 'AD1_BUSY'
Connect: {cpld_ds1@25,  cpld_dsp@30}

For node name 'dp_num'
Connect: {cpld_ds1@10,  cpld_dsp@81}

For node name 'wr_en1'
Connect: {cpld_ds1@38,  cpld_dsp@21}

For node name 'ad_num1'
Connect: {cpld_ds1@26,  cpld_dsp@57}

For node name 'delaytime1'
Connect: {cpld_ds1@34,  cpld_dsp@77}

For node name 'ad_num0'
Connect: {cpld_ds1@44,  cpld_dsp@58}


Project Information                  h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

cpld_dsp@46                       AD0
cpld_dsp@30                       AD1_BUSY
cpld_dsp@29                       AD1_RD
cpld_dsp@44                       AD1
cpld_dsp@27                       AD2_BUSY
cpld_dsp@26                       AD2_RD
cpld_dsp@43                       AD2
cpld_dsp@48                       AD3_BUSY
cpld_dsp@47                       AD3_RD
cpld_dsp@42                       AD3
cpld_dsp@39                       AD4
cpld_dsp@38                       AD5
cpld_dsp@37                       AD6
cpld_dsp@35                       AD7
cpld_dsp@34                       AD8
cpld_dsp@31                       AD9
cpld_dsp@32                       AD10
cpld_dsp@33                       AD11
cpld_dsp@98                       CE1
cpld_dsp@23                       CE2
cpld_dsp@49                       CONV
cpld_dsp@16                       EA0
cpld_dsp@18                       EA1
cpld_dsp@19                       EA2
cpld_dsp@83                       EA6
cpld_dsp@85                       EA7
cpld_dsp@86                       EA8
cpld_dsp@87                       EA9
cpld_dsp@94                       EA10
cpld_dsp@95                       EA11
cpld_dsp@96                       EA12
cpld_dsp@15                       ED0
cpld_dsp@14                       ED1
cpld_dsp@12                       ED2
cpld_dsp@11                       ED3
cpld_dsp@10                       ED4
cpld_dsp@9                        ED5
cpld_dsp@8                        ED6
cpld_dsp@7                        ED7
cpld_dsp@4                        ED8
cpld_dsp@3                        ED9
cpld_dsp@2                        ED10
cpld_dsp@1                        ED11
cpld_dsp@89                       GCLK1
cpld_dsp@92                       GCLK2
cpld_dsp@69                       KEY0
cpld_dsp@67                       KEY1
cpld_dsp@66                       KEY2
cpld_dsp@65                       KEY3
cpld_dsp@63                       KEY4
cpld_dsp@74                       LED0
cpld_dsp@70                       LED1
cpld_dsp@100                      OE1
cpld_dsp@25                       OE2
cpld_dsp@99                       RW1
cpld_dsp@24                       RW2


Project Information                  h:\work\work\jilu\cpld-_jilu\cpld_dsp.rpt

** FILE HIERARCHY **



|lpm_add_sub:1453|
|lpm_add_sub:1453|addcore:adder|
|lpm_add_sub:1453|addcore:adder|addcore:adder0|
|lpm_add_sub:1453|altshift:result_ext_latency_ffs|
|lpm_add_sub:1453|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1453|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1454|
|lpm_add_sub:1454|addcore:adder|
|lpm_add_sub:1454|addcore:adder|addcore:adder0|
|lpm_add_sub:1454|altshift:result_ext_latency_ffs|
|lpm_add_sub:1454|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1454|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1455|
|lpm_add_sub:1455|addcore:adder|
|lpm_add_sub:1455|addcore:adder|addcore:adder1|
|lpm_add_sub:1455|addcore:adder|addcore:adder0|
|lpm_add_sub:1455|altshift:result_ext_latency_ffs|
|lpm_add_sub:1455|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1455|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1456|
|lpm_add_sub:1456|addcore:adder|
|lpm_add_sub:1456|addcore:adder|addcore:adder1|
|lpm_add_sub:1456|addcore:adder|addcore:adder0|
|lpm_add_sub:1456|altshift:result_ext_latency_ffs|
|lpm_add_sub:1456|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1456|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1457|
|lpm_add_sub:1457|addcore:adder|
|lpm_add_sub:1457|addcore:adder|addcore:adder1|
|lpm_add_sub:1457|addcore:adder|addcore:adder0|
|lpm_add_sub:1457|altshift:result_ext_latency_ffs|
|lpm_add_sub:1457|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1457|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1458|
|lpm_add_sub:1458|addcore:adder|
|lpm_add_sub:1458|addcore:adder|addcore:adder1|
|lpm_add_sub:1458|addcore:adder|addcore:adder0|
|lpm_add_sub:1458|altshift:result_ext_latency_ffs|