cpld_dsp.v

cpld max7128s控制3路AD7472采样

module cpld_dsp( EA,ED,AD,CE1,RW1,OE1,CE2,RW2,OE2,AD1_RD,
                 AD1_BUSY,AD2_RD,CONV,AD3_RD,AD3_BUSY,
                 KEY0,KEY1,KEY2,KEY3,KEY4,LED0,LED1,ARM_0,ARM_1,
                 AD2_BUSY,GCLK1,GCLK2
);
input AD1_BUSY,ARM_1,GCLK1,GCLK2,AD3_BUSY;
input AD2_BUSY;
output CE1,RW1,OE1,CE2,RW2,OE2,AD1_RD,AD2_RD,CONV,AD3_RD,LED0,LED1,ARM_0;
input                   KEY0,KEY1,KEY2,KEY3,KEY4;


output [12:0]EA;
input [11:0]AD;
output [11:0]ED;

reg [12:0]stor_num;        //数据计数
reg [1:0]ad_num;           //确定是那个AD
reg dp_num;               //确定双口ram
reg delaytime1;
//reg delaytime2;
//reg delaytime3;
reg CNV;
reg [7:0]num_add ;
reg ad1_ctl;
reg ad2_ctl;
reg ad3_ctl;
reg [1:0]dp_ctl;
//reg [1:0]dp2_ctl;
//reg [1:0]dp3_ctl;
reg[1:0] wr_en;          //双口RAM写入控制
reg wr_en_ctl;
reg int_0;
//reg [11:0]data_buf;

assign CONV = CNV || CNV;
assign ED = AD;
assign EA = stor_num;         //DP地址线       

assign OE1 = 1'b1;
assign OE2 = 1'b1;
assign LED1 = 0;
assign LED0 = 0;
assign ARM_0 = int_0;   //申请中断

assign CE1 = dp_ctl[0];
assign RW1 = dp_ctl[0];
assign CE2 = dp_ctl[1];
assign RW2 = dp_ctl[1];

assign AD1_RD =ad1_ctl;
assign AD2_RD =ad2_ctl;
assign AD3_RD =ad3_ctl;
/*
assign CE1 = 1'b1;
assign RW1 = 1'b1;
assign CE2 = 1'b1;
assign RW2 = 1'b1;

assign AD1_RD =1'b1;
assign AD2_RD =1'b1;
assign AD3_RD =1'b1;
*/
always@(negedge ARM_1 or negedge wr_en_ctl)
begin
   if(wr_en_ctl == 0)
     wr_en = wr_en +1;                 //双口RAM写入控制，1允许写入，0禁止写入
   else
     wr_en = wr_en - 1;
end
always@(negedge GCLK1)
begin
 if(wr_en < 2)                           //允许写入
  if(AD1_BUSY == 0)                  //转换完毕
       if(dp_num ==0)
       begin
          dp_ctl[1] <= 1;                //片选DP1，置DP2高阻
          if(stor_num <1365)
          begin
            int_0 <= 1'b1;               //中断标志
            wr_en_ctl <=1;               //DP写满标志，0有