sent.tan.rpt

来自「用verilog实现的串口收发数据程序」· RPT 代码 · 共 176 行 · 第 1/5 页

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK                          ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                         ; To                                                                                                                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 95.00 MHz ( period = 10.526 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[4]  ; CLK        ; CLK      ; None                        ; None                      ; 10.265 ns               ;
; N/A                                     ; 95.00 MHz ( period = 10.526 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[5]  ; CLK        ; CLK      ; None                        ; None                      ; 10.265 ns               ;
; N/A                                     ; 95.00 MHz ( period = 10.526 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[1]  ; CLK        ; CLK      ; None                        ; None                      ; 10.265 ns               ;
; N/A                                     ; 95.00 MHz ( period = 10.526 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; CLK        ; CLK      ; None                        ; None                      ; 10.265 ns               ;
; N/A                                     ; 95.00 MHz ( period = 10.526 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[2]  ; CLK        ; CLK      ; None                        ; None                      ; 10.265 ns               ;
; N/A                                     ; 95.00 MHz ( period = 10.526 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[3]  ; CLK        ; CLK      ; None                        ; None                      ; 10.265 ns               ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[12] ; CLK        ; CLK      ; None                        ; None                      ; 10.062 ns               ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[11] ; CLK        ; CLK      ; None                        ; None                      ; 10.062 ns               ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[6]  ; CLK        ; CLK      ; None                        ; None                      ; 10.062 ns               ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[7]  ; CLK        ; CLK      ; None                        ; None                      ; 10.062 ns               ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[8]  ; CLK        ; CLK      ; None                        ; None                      ; 10.062 ns               ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[0]  ; sld_signaltap:sent|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_h29:auto_generated|safe_q[9]  ; CLK        ; CLK      ; None                        ; None                      ; 10.062 ns               ;