rec.map.rpt

用verilog实现的串口收发数据程序

Analysis & Synthesis report for rec
Fri Dec 14 23:12:17 2007
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Parameter Settings for Inferred Entity Instance: sld_signaltap:rec
 12. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 13. SignalTap II Logic Analyzer Settings
 14. Analysis & Synthesis Equations
 15. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Dec 14 23:12:17 2007         ;
; Quartus II Version          ; 5.0 Build 171 11/03/2005 SP 2 SJ Full Version ;
; Revision Name               ; rec                                           ;
; Top-level Entity Name       ; rec                                           ;
; Family                      ; Cyclone                                       ;
; Total logic elements        ; 445                                           ;
; Total pins                  ; 18                                            ;
; Total virtual pins          ; 0                                             ;
; Total memory bits           ; 45,056                                        ;
; Total PLLs                  ; 0                                             ;
+-----------------------------+-----------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                     ;
+--------------------------------------------------------------------+--------------+---------------+
; Option                                                             ; Setting      ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device                                                             ; EP1C6Q240C8  ;               ;
; Top-level entity name                                              ; rec          ; rec           ;
; Family name                                                        ; Cyclone      ; Stratix       ;
; Use smart compilation                                              ; Off          ; Off           ;
; Restructure Multiplexers                                           ; Auto         ; Auto          ;
; Create Debugging Nodes for IP Cores                                ; off          ; off           ;
; Preserve fewer node names                                          ; On           ; On            ;
; Disable OpenCore Plus hardware evaluation                          ; Off          ; Off           ;
; Verilog Version                                                    ; Verilog_2001 ; Verilog_2001  ;
; VHDL Version                                                       ; VHDL93       ; VHDL93        ;