test_rec.tan.qmsg

用verilog实现的串口收发数据程序

{ "Info" "ITDB_TSU_RESULT" "state\[1\]~reg0 rxd clk 8.936 ns register " "Info: tsu for register \"state\[1\]~reg0\" (data pin = \"rxd\", clock pin = \"clk\") is 8.936 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.824 ns + Longest pin register " "Info: + Longest pin to register delay is 11.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_213 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_213; Fanout = 4; PIN Node = 'rxd'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { rxd } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.726 ns) + CELL(0.292 ns) 8.493 ns state~536 2 COMB LC_X16_Y11_N4 11 " "Info: 2: + IC(6.726 ns) + CELL(0.292 ns) = 8.493 ns; Loc. = LC_X16_Y11_N4; Fanout = 11; COMB Node = 'state~536'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "7.018 ns" { rxd state~536 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.590 ns) 10.323 ns state\[1\]~537 3 COMB LC_X14_Y11_N8 2 " "Info: 3: + IC(1.240 ns) + CELL(0.590 ns) = 10.323 ns; Loc. = LC_X14_Y11_N8; Fanout = 2; COMB Node = 'state\[1\]~537'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.830 ns" { state~536 state[1]~537 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.309 ns) 11.824 ns state\[1\]~reg0 4 REG LC_X16_Y11_N1 12 " "Info: 4: + IC(1.192 ns) + CELL(0.309 ns) = 11.824 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state\[1\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.501 ns" { state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.666 ns 22.55 % " "Info: Total cell delay = 2.666 ns ( 22.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.158 ns 77.45 % " "Info: Total interconnect delay = 9.158 ns ( 77.45 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "11.824 ns" { rxd state~536 state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.824 ns" { rxd rxd~out0 state~536 state[1]~537 state[1]~reg0 } { 0.000ns 0.000ns 6.726ns 1.240ns 1.192ns } { 0.000ns 1.475ns 0.292ns 0.590ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { clk } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns state\[1\]~reg0 2 REG LC_X16_Y11_N1 12 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state\[1\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.456 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[1]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "11.824 ns" { rxd state~536 state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.824 ns" { rxd rxd~out0 state~536 state[1]~537 state[1]~reg0 } { 0.000ns 0.000ns 6.726ns 1.240ns 1.192ns } { 0.000ns 1.475ns 0.292ns 0.590ns 0.309ns } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[1]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk state\[0\] state\[0\]~reg0 7.887 ns register " "Info: tco from clock \"clk\" to destination pin \"state\[0\]\" through register \"state\[0\]~reg0\" is 7.887 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { clk } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns state\[0\]~reg0 2 REG LC_X14_Y11_N9 7 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.456 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.738 ns + Longest register pin " "Info: + Longest register to pin delay is 4.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\]~reg0 1 REG LC_X14_Y11_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { state[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.630 ns) + CELL(2.108 ns) 4.738 ns state\[0\] 2 PIN PIN_215 0 " "Info: 2: + IC(2.630 ns) + CELL(2.108 ns) = 4.738 ns; Loc. = PIN_215; Fanout = 0; PIN Node = 'state\[0\]'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "4.738 ns" { state[0]~reg0 state[0] } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 44.49 % " "Info: Total cell delay = 2.108 ns ( 44.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.630 ns 55.51 % " "Info: Total interconnect delay = 2.630 ns ( 55.51 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "4.738 ns" { state[0]~reg0 state[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.738 ns" { state[0]~reg0 state[0] } { 0.000ns 2.630ns } { 0.000ns 2.108ns } } }  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "4.738 ns" { state[0]~reg0 state[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.738 ns" { state[0]~reg0 state[0] } { 0.000ns 2.630ns } { 0.000ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "data_out\[0\]~reg0 rxd clk -5.090 ns register " "Info: th for register \"data_out\[0\]~reg0\" (data pin = \"rxd\", clock pin = \"clk\") is -5.090 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { clk } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns data_out\[0\]~reg0 2 REG LC_X13_Y11_N9 2 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X13_Y11_N9; Fanout = 2; REG Node = 'data_out\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.456 ns" { clk data_out[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 data_out[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.030 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.030 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns rxd 1 PIN PIN_213 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_213; Fanout = 4; PIN Node = 'rxd'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { rxd } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.246 ns) + CELL(0.309 ns) 8.030 ns data_out\[0\]~reg0 2 REG LC_X13_Y11_N9 2 " "Info: 2: + IC(6.246 ns) + CELL(0.309 ns) = 8.030 ns; Loc. = LC_X13_Y11_N9; Fanout = 2; REG Node = 'data_out\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "6.555 ns" { rxd data_out[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 22.22 % " "Info: Total cell delay = 1.784 ns ( 22.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.246 ns 77.78 % " "Info: Total interconnect delay = 6.246 ns ( 77.78 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "8.030 ns" { rxd data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.030 ns" { rxd rxd~out0 data_out[0]~reg0 } { 0.000ns 0.000ns 6.246ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 data_out[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "8.030 ns" { rxd data_out[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.030 ns" { rxd rxd~out0 data_out[0]~reg0 } { 0.000ns 0.000ns 6.246ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 12 21:32:42 2007 " "Info: Processing ended: Fri Oct 12 21:32:42 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}