test_rec.tan.qmsg

用verilog实现的串口收发数据程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 12 21:32:41 2007 " "Info: Processing started: Fri Oct 12 21:32:41 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off test_rec -c test_rec --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test_rec -c test_rec --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 2 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state\[0\]~reg0 register state\[1\]~reg0 201.37 MHz 4.966 ns Internal " "Info: Clock \"clk\" has Internal fmax of 201.37 MHz between source register \"state\[0\]~reg0\" and destination register \"state\[1\]~reg0\" (period= 4.966 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.705 ns + Longest register register " "Info: + Longest register to register delay is 4.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\]~reg0 1 REG LC_X14_Y11_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { state[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.260 ns) + CELL(0.114 ns) 1.374 ns state~536 2 COMB LC_X16_Y11_N4 11 " "Info: 2: + IC(1.260 ns) + CELL(0.114 ns) = 1.374 ns; Loc. = LC_X16_Y11_N4; Fanout = 11; COMB Node = 'state~536'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.374 ns" { state[0]~reg0 state~536 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.240 ns) + CELL(0.590 ns) 3.204 ns state\[1\]~537 3 COMB LC_X14_Y11_N8 2 " "Info: 3: + IC(1.240 ns) + CELL(0.590 ns) = 3.204 ns; Loc. = LC_X14_Y11_N8; Fanout = 2; COMB Node = 'state\[1\]~537'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.830 ns" { state~536 state[1]~537 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.309 ns) 4.705 ns state\[1\]~reg0 4 REG LC_X16_Y11_N1 12 " "Info: 4: + IC(1.192 ns) + CELL(0.309 ns) = 4.705 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state\[1\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.501 ns" { state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.013 ns 21.53 % " "Info: Total cell delay = 1.013 ns ( 21.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.692 ns 78.47 % " "Info: Total interconnect delay = 3.692 ns ( 78.47 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "4.705 ns" { state[0]~reg0 state~536 state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.705 ns" { state[0]~reg0 state~536 state[1]~537 state[1]~reg0 } { 0.000ns 1.260ns 1.240ns 1.192ns } { 0.000ns 0.114ns 0.590ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.925 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { clk } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns state\[1\]~reg0 2 REG LC_X16_Y11_N1 12 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X16_Y11_N1; Fanout = 12; REG Node = 'state\[1\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.456 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[1]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 22 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "" { clk } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns state\[0\]~reg0 2 REG LC_X14_Y11_N9 7 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X14_Y11_N9; Fanout = 7; REG Node = 'state\[0\]~reg0'" {  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "1.456 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[1]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "test_rec.v" "" { Text "F:/test_rec/test_rec.v" 84 -1 0 } }  } 0}  } { { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "4.705 ns" { state[0]~reg0 state~536 state[1]~537 state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.705 ns" { state[0]~reg0 state~536 state[1]~537 state[1]~reg0 } { 0.000ns 1.260ns 1.240ns 1.192ns } { 0.000ns 0.114ns 0.590ns 0.309ns } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[1]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/test_rec/db/test_rec_cmp.qrpt" "" { Report "F:/test_rec/db/test_rec_cmp.qrpt" Compiler "test_rec" "UNKNOWN" "V1" "F:/test_rec/db/test_rec.quartus_db" { Floorplan "F:/test_rec/" "" "2.925 ns" { clk state[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 state[0]~reg0 } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}