liushui.fit.rpt

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· RPT 代码 · 共 444 行 · 第 1/5 页

+--------------------------------------------------------------------------------------------------+
; I/O Standard                                                                                     ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; LVTTL        ; -          ; 1                    ; 0                 ; 0                 ; 1     ;
+--------------+------------+----------------------+-------------------+-------------------+-------+


+--------------------------------------------------------------------+
; Dedicated Inputs I/O                                               ;
+------+-------+-------+-------+--------------+------------+---------+
; Name ; Pin # ; Type  ; VCCIO ; I/O Standard ; Input Vref ; Current ;
+------+-------+-------+-------+--------------+------------+---------+
; clk  ; 87    ; Input ; --    ; LVTTL        ; -          ; 0 mA    ;
+------+-------+-------+-------+--------------+------------+---------+


+-----------------------------------------------+
; Output Pin Default Load For Reported TCO      ;
+--------------+-------+------------------------+
; I/O Standard ; Load  ; Termination Resistance ;
+--------------+-------+------------------------+
; LVTTL        ; 10 pF ; Not Available          ;
; LVCMOS       ; 10 pF ; Not Available          ;
; 3.3-V PCI    ; 10 pF ; 25 Ohm (Parallel)      ;
; 2.5 V        ; 10 pF ; Not Available          ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+-------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                               ;
+------------------------------+------------+------+----------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name              ;
+------------------------------+------------+------+----------------------------------+
; |liushui                     ; 35         ; 14   ; |liushui                         ;
;    |lpm_counter:count_rtl_0| ; 27         ; 0    ; |liushui|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+----------------------------------+


+--------------------------------------------------------------------------------------+
; Control Signals                                                                      ;
+------+----------+---------+-------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------+----------+---------+-------+--------+----------------------+------------------+
; clk  ; PIN_87   ; 27      ; Clock ; yes    ; On                   ; --               ;
+------+----------+---------+-------+--------+----------------------+------------------+


+---------------------------------------------------------------------+
; Global & Other Fast Signals                                         ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk  ; PIN_87   ; 27      ; On                   ; --               ;
+------+----------+---------+----------------------+------------------+


+--------------------------------------------+
; Non-Global High Fan-Out Signals            ;
+----------------------------------+---------+
; Name                             ; Fan-Out ;
+----------------------------------+---------+
; reset                            ; 27      ;
; lpm_counter:count_rtl_0|dffs[0]  ; 27      ;
; lpm_counter:count_rtl_0|dffs[1]  ; 26      ;
; lpm_counter:count_rtl_0|dffs[2]  ; 25      ;
; lpm_counter:count_rtl_0|dffs[3]  ; 24      ;
; lpm_counter:count_rtl_0|dffs[4]  ; 23      ;
; lpm_counter:count_rtl_0|dffs[5]  ; 22      ;
; lpm_counter:count_rtl_0|dffs[6]  ; 21      ;
; lpm_counter:count_rtl_0|dffs[7]  ; 20      ;
; lpm_counter:count_rtl_0|dffs[8]  ; 19      ;
; lpm_counter:count_rtl_0|dffs[9]  ; 18      ;
; lpm_counter:count_rtl_0|dffs[10] ; 17      ;
; lpm_counter:count_rtl_0|dffs[11] ; 16      ;
; lpm_counter:count_rtl_0|dffs[12] ; 15      ;
; lpm_counter:count_rtl_0|dffs[13] ; 14      ;
; lpm_counter:count_rtl_0|dffs[14] ; 13      ;
; lpm_counter:count_rtl_0|dffs[15] ; 12      ;
; lpm_counter:count_rtl_0|dffs[24] ; 11      ;
; lpm_counter:count_rtl_0|dffs[16] ; 11      ;
; lpm_counter:count_rtl_0|dffs[25] ; 10      ;
; lpm_counter:count_rtl_0|dffs[17] ; 10      ;
; lpm_counter:count_rtl_0|dffs[26] ; 9       ;
; lpm_counter:count_rtl_0|dffs[18] ; 9       ;
; lpm_counter:count_rtl_0|dffs[19] ; 8       ;