hongwai.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 23:45:42 2007 " "Info: Processing started: Thu Jul 05 23:45:42 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off hongwai -c hongwai " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off hongwai -c hongwai" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "jie led\[6\] 10.100 ns Longest " "Info: Longest tpd from source pin \"jie\" to destination pin \"led\[6\]\" is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns jie 1 PIN PIN_70 4 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_70; Fanout = 4; PIN Node = 'jie'" {  } { { "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" "" { Report "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" Compiler "hongwai" "UNKNOWN" "V1" "C:/altera/quartus50/hongwai/db/hongwai.quartus_db" { Floorplan "C:/altera/quartus50/hongwai/" "" "" { jie } "NODE_NAME" } "" } } { "hongwai.v" "" { Text "C:/altera/quartus50/hongwai/hongwai.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 8.500 ns jie~14 2 COMB LC37 1 " "Info: 2: + IC(2.700 ns) + CELL(4.400 ns) = 8.500 ns; Loc. = LC37; Fanout = 1; COMB Node = 'jie~14'" {  } { { "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" "" { Report "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" Compiler "hongwai" "UNKNOWN" "V1" "C:/altera/quartus50/hongwai/db/hongwai.quartus_db" { Floorplan "C:/altera/quartus50/hongwai/" "" "7.100 ns" { jie jie~14 } "NODE_NAME" } "" } } { "hongwai.v" "" { Text "C:/altera/quartus50/hongwai/hongwai.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.100 ns led\[6\] 3 PIN PIN_23 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.100 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'led\[6\]'" {  } { { "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" "" { Report "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" Compiler "hongwai" "UNKNOWN" "V1" "C:/altera/quartus50/hongwai/db/hongwai.quartus_db" { Floorplan "C:/altera/quartus50/hongwai/" "" "1.600 ns" { jie~14 led[6] } "NODE_NAME" } "" } } { "hongwai.v" "" { Text "C:/altera/quartus50/hongwai/hongwai.v" 2 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 73.27 % " "Info: Total cell delay = 7.400 ns ( 73.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 26.73 % " "Info: Total interconnect delay = 2.700 ns ( 26.73 % )" {  } {  } 0}  } { { "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" "" { Report "C:/altera/quartus50/hongwai/db/hongwai_cmp.qrpt" Compiler "hongwai" "UNKNOWN" "V1" "C:/altera/quartus50/hongwai/db/hongwai.quartus_db" { Floorplan "C:/altera/quartus50/hongwai/" "" "10.100 ns" { jie jie~14 led[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.100 ns" { jie jie~out jie~14 led[6] } { 0.000ns 0.000ns 2.700ns 0.000ns } { 0.000ns 1.400ns 4.400ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:45:42 2007 " "Info: Processing ended: Thu Jul 05 23:45:42 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}