hongwai.fit.eqn

通过VERILOG HDL语言使用CPLD连接PS2键盘

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--A1L6 is jie~8 at LC33
A1L6_or_out = !jie;
A1L6 = A1L6_or_out;


--A1L7 is jie~10 at LC62
A1L7_or_out = !jie;
A1L7 = A1L7_or_out;


--A1L8 is jie~12 at LC59
A1L8_or_out = !jie;
A1L8 = A1L8_or_out;


--A1L9 is jie~14 at LC37
A1L9_or_out = !jie;
A1L9 = A1L9_or_out;


--~VCC~0 is ~VCC~0 at LC61
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1 at LC64
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~VCC~2 is ~VCC~2 at LC35
~VCC~2_or_out = GND;
~VCC~2 = !(~VCC~2_or_out);


--~VCC~3 is ~VCC~3 at LC38
~VCC~3_or_out = GND;
~VCC~3 = !(~VCC~3_or_out);


--jie is jie at PIN_70
--operation mode is input

jie = INPUT();


--led[1] is led[1] at PIN_29
--operation mode is output

led[1] = OUTPUT(~VCC~0);


--led[3] is led[3] at PIN_27
--operation mode is output

led[3] = OUTPUT(~VCC~1);


--led[5] is led[5] at PIN_24
--operation mode is output

led[5] = OUTPUT(~VCC~2);


--led[7] is led[7] at PIN_22
--operation mode is output

led[7] = OUTPUT(~VCC~3);


--led[0] is led[0] at PIN_30
--operation mode is output

led[0] = OUTPUT(A1L8);


--led[2] is led[2] at PIN_28
--operation mode is output

led[2] = OUTPUT(A1L7);


--led[4] is led[4] at PIN_25
--operation mode is output

led[4] = OUTPUT(A1L6);


--led[6] is led[6] at PIN_23
--operation mode is output

led[6] = OUTPUT(A1L9);