jianpan1.tan.summary

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· SUMMARY 代码 · 共 47 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 36.200 ns
From           : lpm_counter:count_rtl_0|dffs[24]
To             : lddat[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 31.500 ns
From           : a[1]
To             : lddat[0]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 97.09 MHz ( period = 10.300 ns )
From           : lpm_counter:count_rtl_0|dffs[0]
To             : lpm_counter:count_rtl_0|dffs[23]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------