jianpan1.map.summary

通过VERILOG HDL语言使用CPLD连接PS2键盘

Flow Status : Successful - Thu Jul 05 23:52:36 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : jianpan1
Top-level Entity Name : jianpan1
Family : MAX3000A
Device : EPM3128ATC100-10
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 68
Total pins : 23