jianpan1.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘

; Maximum fan-out      ; 25                   ;
; Total fan-out        ; 566                  ;
; Average fan-out      ; 6.22                 ;
+----------------------+----------------------+


+--------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                  ;
+------------------------------+------------+------+-----------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name               ;
+------------------------------+------------+------+-----------------------------------+
; |jianpan1                    ; 68         ; 23   ; |jianpan1                         ;
;    |lpm_counter:count_rtl_0| ; 25         ; 0    ; |jianpan1|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+-----------------------------------+


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; bb[0]                                         ;    ;
; bb[1]                                         ;    ;
; bb[2]                                         ;    ;
; bb[3]                                         ;    ;
; ledd.0100                                     ;    ;
; ledd.0001                                     ;    ;
; ledd.1101                                     ;    ;
; ledd.1011                                     ;    ;
; ledd.0101                                     ;    ;
; ledd.0110                                     ;    ;
; ledd.1100                                     ;    ;
; ledd.1110                                     ;    ;
; ledd.1111                                     ;    ;
; ledd.0010                                     ;    ;
; ledd.0111                                     ;    ;
; ledd.1010                                     ;    ;
; ledd.0011                                     ;    ;
; ledd.1001                                     ;    ;
; ledd.0000                                     ;    ;
; Number of user-specified and inferred latches ; 19 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:count_rtl_0 ;
+------------------------+----------+--------------------------------------+
; Parameter Name         ; Value    ; Type                                 ;
+------------------------+----------+--------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                       ;
; LPM_WIDTH              ; 28       ; Untyped                              ;
; LPM_DIRECTION          ; UP       ; Untyped                              ;
; LPM_MODULUS            ; 0        ; Untyped                              ;
; LPM_AVALUE             ; UNUSED   ; Untyped                              ;
; LPM_SVALUE             ; UNUSED   ; Untyped                              ;
; DEVICE_FAMILY          ; MAX3000A ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                              ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                   ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                   ;
; CARRY_CNT_EN           ; SMART    ; Untyped                              ;
; LABWIDE_SCLR           ; ON       ; Untyped                              ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                              ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                              ;
+------------------------+----------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/keyarray/jianpan1.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jul 05 23:52:32 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jianpan1 -c jianpan1
Info: Found 1 design units, including 1 entities, in source file jianpan1.v
    Info: Found entity 1: jianpan1
Info: Elaborating entity "jianpan1" for the top level hierarchy
Warning: Verilog HDL Always Construct warning at jianpan1.v(17): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at jianpan1.v(17): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at jianpan1.v(15): variable "bb" may not be assigned a new value in every possible path through the Always Construct.  Variable "bb" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at jianpan1.v(28): truncated value with size 32 to match size of target (28)
Warning: Verilog HDL assignment warning at jianpan1.v(33): truncated value with size 32 to match size of target (28)
Warning: Verilog HDL Always Construct warning at jianpan1.v(40): variable "a" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at jianpan1.v(41): variable "bb" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at jianpan1.v(43): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at jianpan1.v(57): variable "bb" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at jianpan1.v(59): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at jianpan1.v(67): variable "bb" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at jianpan1.v(69): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at jianpan1.v(78): variable "bb" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at jianpan1.v(80): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at jianpan1.v(38): variable "ledd" may not be assigned a new value in every possible path through the Always Construct.  Variable "ledd" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at jianpan1.v(91): variable "ledd" is read inside the Always Construct but isn't in the Always Construct's Event Control
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=28) from the following logic: "count[0]~28"
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lddat[7]" stuck at VCC
    Warning: Pin "wei[0]" stuck at VCC
    Warning: Pin "wei[1]" stuck at GND
    Warning: Pin "wei[2]" stuck at GND
    Warning: Pin "wei[3]" stuck at GND
    Warning: Pin "wei[4]" stuck at GND
    Warning: Pin "wei[5]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 91 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 18 output pins
    Info: Implemented 68 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Thu Jul 05 23:52:36 2007
    Info: Elapsed time: 00:00:05