📄 jishu2.tan.qmsg
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "duanreg\[2\]~345 " "Info: Node \"duanreg\[2\]~345\"" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0} } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "duanreg\[1\]~341 " "Info: Node \"duanreg\[1\]~341\"" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0} } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "duanreg\[0\]~337 " "Info: Node \"duanreg\[0\]~337\"" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0} } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 2 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counta\[25\] register counta\[29\] 53.76 MHz 18.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 53.76 MHz between source register \"counta\[25\]\" and destination register \"counta\[29\]\" (period= 18.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.100 ns + Longest register register " "Info: + Longest register to register delay is 14.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counta\[25\] 1 REG LC33 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 63; REG Node = 'counta\[25\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { counta[25] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.300 ns) 4.300 ns reduce_nor~14 2 COMB LC25 1 " "Info: 2: + IC(3.000 ns) + CELL(1.300 ns) = 4.300 ns; Loc. = LC25; Fanout = 1; COMB Node = 'reduce_nor~14'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "4.300 ns" { counta[25] reduce_nor~14 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 8.300 ns reduce_nor~7 3 COMB LC26 31 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 8.300 ns; Loc. = LC26; Fanout = 31; COMB Node = 'reduce_nor~7'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "4.000 ns" { reduce_nor~14 reduce_nor~7 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 14.100 ns counta\[29\] 4 REG LC52 29 " "Info: 4: + IC(2.700 ns) + CELL(3.100 ns) = 14.100 ns; Loc. = LC52; Fanout = 29; REG Node = 'counta\[29\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "5.800 ns" { reduce_nor~7 counta[29] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.400 ns 59.57 % " "Info: Total cell delay = 8.400 ns ( 59.57 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns 40.43 % " "Info: Total interconnect delay = 5.700 ns ( 40.43 % )" { } { } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "14.100 ns" { counta[25] reduce_nor~14 reduce_nor~7 counta[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.100 ns" { counta[25] reduce_nor~14 reduce_nor~7 counta[29] } { 0.000ns 3.000ns 0.000ns 2.700ns } { 0.000ns 1.300ns 4.000ns 3.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 32 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 32; CLK Node = 'clk'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { clk } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counta\[29\] 2 REG LC52 29 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC52; Fanout = 29; REG Node = 'counta\[29\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "0.900 ns" { clk counta[29] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[29] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 32 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 32; CLK Node = 'clk'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { clk } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counta\[25\] 2 REG LC33 63 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC33; Fanout = 63; REG Node = 'counta\[25\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "0.900 ns" { clk counta[25] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[25] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[29] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[25] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "14.100 ns" { counta[25] reduce_nor~14 reduce_nor~7 counta[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "14.100 ns" { counta[25] reduce_nor~14 reduce_nor~7 counta[29] } { 0.000ns 3.000ns 0.000ns 2.700ns } { 0.000ns 1.300ns 4.000ns 3.100ns } } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[29] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[29] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[25] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk duan\[5\] counta\[26\] 29.000 ns register " "Info: tco from clock \"clk\" to destination pin \"duan\[5\]\" through register \"counta\[26\]\" is 29.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 32 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 32; CLK Node = 'clk'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { clk } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counta\[26\] 2 REG LC22 55 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC22; Fanout = 55; REG Node = 'counta\[26\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "0.900 ns" { clk counta[26] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[26] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[26] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.000 ns + Longest register pin " "Info: + Longest register to pin delay is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counta\[26\] 1 REG LC22 55 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC22; Fanout = 55; REG Node = 'counta\[26\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { counta[26] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(4.400 ns) 7.400 ns reduce_or~736 2 COMB LC6 30 " "Info: 2: + IC(3.000 ns) + CELL(4.400 ns) = 7.400 ns; Loc. = LC6; Fanout = 30; COMB Node = 'reduce_or~736'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "7.400 ns" { counta[26] reduce_or~736 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 15.400 ns duanreg\[5\]~357 3 COMB LOOP LC3 7 " "Info: 3: + IC(0.000 ns) + CELL(8.000 ns) = 15.400 ns; Loc. = LC3; Fanout = 7; COMB LOOP Node = 'duanreg\[5\]~357'" { { "Info" "ITDB_PART_OF_SCC" "duanreg\[5\]~357 LC3 " "Info: Loc. = LC3; Node \"duanreg\[5\]~357\"" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { duanreg[5]~357 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_PART_OF_SCC" "duanreg\[5\]~383 LC2 " "Info: Loc. = LC2; Node \"duanreg\[5\]~383\"" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { duanreg[5]~383 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_PART_OF_SCC" "duanreg\[5\]~384 LC1 " "Info: Loc. = LC1; Node \"duanreg\[5\]~384\"" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { duanreg[5]~384 } "NODE_NAME" } "" } } } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { duanreg[5]~357 } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { duanreg[5]~383 } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "" { duanreg[5]~384 } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "8.000 ns" { reduce_or~736 duanreg[5]~357 } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 22.400 ns duanreg\[5\]~386 4 COMB LC13 1 " "Info: 4: + IC(2.600 ns) + CELL(4.400 ns) = 22.400 ns; Loc. = LC13; Fanout = 1; COMB Node = 'duanreg\[5\]~386'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "7.000 ns" { duanreg[5]~357 duanreg[5]~386 } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 24.000 ns duan\[5\] 5 PIN PIN_94 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 24.000 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'duan\[5\]'" { } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "1.600 ns" { duanreg[5]~386 duan[5] } "NODE_NAME" } "" } } { "jishu2.v" "" { Text "C:/altera/quartus50/0-99COUNTER/jishu2.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.400 ns 76.67 % " "Info: Total cell delay = 18.400 ns ( 76.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns 23.33 % " "Info: Total interconnect delay = 5.600 ns ( 23.33 % )" { } { } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "24.000 ns" { counta[26] reduce_or~736 duanreg[5]~357 duanreg[5]~386 duan[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { counta[26] reduce_or~736 duanreg[5]~357 duanreg[5]~386 duan[5] } { 0.000ns 3.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 4.400ns 8.000ns 4.400ns 1.600ns } } } } 0} } { { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "3.400 ns" { clk counta[26] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counta[26] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" "" { Report "C:/altera/quartus50/0-99COUNTER/db/jishu2_cmp.qrpt" Compiler "jishu2" "UNKNOWN" "V1" "C:/altera/quartus50/0-99COUNTER/db/jishu2.quartus_db" { Floorplan "C:/altera/quartus50/0-99COUNTER/" "" "24.000 ns" { counta[26] reduce_or~736 duanreg[5]~357 duanreg[5]~386 duan[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { counta[26] reduce_or~736 duanreg[5]~357 duanreg[5]~386 duan[5] } { 0.000ns 3.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 4.400ns 8.000ns 4.400ns 1.600ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 22:49:55 2007 " "Info: Processing ended: Thu Jul 05 22:49:55 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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