ps2.tan.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘

; N/A           ; None        ; -2.400 ns ; key_clock ; filter[0]         ; sys_clock ;
; N/A           ; None        ; -2.400 ns ; key_clock ; filter[7]         ; sys_clock ;
; N/A           ; None        ; -2.400 ns ; key_clock ; filter[6]         ; sys_clock ;
; N/A           ; None        ; -2.400 ns ; key_clock ; filter[3]         ; sys_clock ;
; N/A           ; None        ; -2.400 ns ; key_clock ; filter[2]         ; sys_clock ;
+---------------+-------------+-----------+-----------+-------------------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jul 06 00:07:22 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ps2 -c ps2
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "sys_clock" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "scan_end~reg0" as buffer
    Info: Detected ripple clock "smooth_key_clock" as buffer
Info: Clock "sys_clock" has Internal fmax of 97.09 MHz between source register "save_scan_code[6]" and destination register "save_scan_code[6]" (period= 10.3 ns)
    Info: + Longest register to register delay is 5.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code[6]'
        Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code[6]'
        Info: Total cell delay = 3.100 ns ( 53.45 % )
        Info: Total interconnect delay = 2.700 ns ( 46.55 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "sys_clock" to destination register is 9.800 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
            Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'
            Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code[6]'
            Info: Total cell delay = 7.200 ns ( 73.47 % )
            Info: Total interconnect delay = 2.600 ns ( 26.53 % )
        Info: - Longest clock path from clock "sys_clock" to source register is 9.800 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
            Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'
            Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC2; Fanout = 4; REG Node = 'save_scan_code[6]'
            Info: Total cell delay = 7.200 ns ( 73.47 % )
            Info: Total interconnect delay = 2.600 ns ( 26.53 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Warning: Circuit may not operate. Detected 9 non-operational path(s) clocked by clock "sys_clock" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "save_scan_code[9]" and destination pin or register "scan_parity~reg0" for clock "sys_clock" (Hold time is 600 ps)
    Info: + Largest clock skew is 6.600 ns
        Info: + Longest clock path from clock "sys_clock" to destination register is 16.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
            Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'
            Info: 3: + IC(2.600 ns) + CELL(3.800 ns) = 11.400 ns; Loc. = LC1; Fanout = 10; REG Node = 'scan_end~reg0'
            Info: 4: + IC(2.800 ns) + CELL(2.200 ns) = 16.400 ns; Loc. = LC3; Fanout = 1; REG Node = 'scan_parity~reg0'
            Info: Total cell delay = 11.000 ns ( 67.07 % )
            Info: Total interconnect delay = 5.400 ns ( 32.93 % )
        Info: - Shortest clock path from clock "sys_clock" to source register is 9.800 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
            Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'
            Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC16; Fanout = 4; REG Node = 'save_scan_code[9]'
            Info: Total cell delay = 7.200 ns ( 73.47 % )
            Info: Total interconnect delay = 2.600 ns ( 26.53 % )
    Info: - Micro clock to output delay of source is 1.600 ns
    Info: - Shortest register to register delay is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'save_scan_code[9]'
        Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 5.700 ns; Loc. = LC3; Fanout = 1; REG Node = 'scan_parity~reg0'
        Info: Total cell delay = 3.100 ns ( 54.39 % )
        Info: Total interconnect delay = 2.600 ns ( 45.61 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "filter[9]" (data pin = "key_clock", clock pin = "sys_clock") is 6.600 ns
    Info: + Longest pin to register delay is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_68; Fanout = 10; PIN Node = 'key_clock'
        Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 7.100 ns; Loc. = LC20; Fanout = 2; REG Node = 'filter[9]'
        Info: Total cell delay = 4.500 ns ( 63.38 % )
        Info: Total interconnect delay = 2.600 ns ( 36.62 % )
    Info: + Micro setup delay of destination is 2.900 ns
    Info: - Shortest clock path from clock "sys_clock" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC20; Fanout = 2; REG Node = 'filter[9]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: tco from clock "sys_clock" to destination pin "scan_code[6]" through register "scan_code[6]~reg0" is 19.600 ns
    Info: + Longest clock path from clock "sys_clock" to source register is 16.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
        Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'
        Info: 3: + IC(2.600 ns) + CELL(3.800 ns) = 11.400 ns; Loc. = LC1; Fanout = 10; REG Node = 'scan_end~reg0'
        Info: 4: + IC(2.800 ns) + CELL(2.200 ns) = 16.400 ns; Loc. = LC61; Fanout = 1; REG Node = 'scan_code[6]~reg0'
        Info: Total cell delay = 11.000 ns ( 67.07 % )
        Info: Total interconnect delay = 5.400 ns ( 32.93 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 1.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC61; Fanout = 1; REG Node = 'scan_code[6]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_29; Fanout = 0; PIN Node = 'scan_code[6]'
        Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: th for register "save_scan_code[1]" (data pin = "key_data", clock pin = "sys_clock") is 4.000 ns
    Info: + Longest clock path from clock "sys_clock" to destination register is 9.800 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'
        Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC11; Fanout = 17; REG Node = 'smooth_key_clock'
        Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC10; Fanout = 4; REG Node = 'save_scan_code[1]'
        Info: Total cell delay = 7.200 ns ( 73.47 % )
        Info: Total interconnect delay = 2.600 ns ( 26.53 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 7.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_67; Fanout = 18; PIN Node = 'key_data'
        Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 7.100 ns; Loc. = LC10; Fanout = 4; REG Node = 'save_scan_code[1]'
        Info: Total cell delay = 4.500 ns ( 63.38 % )
        Info: Total interconnect delay = 2.600 ns ( 36.62 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Fri Jul 06 00:07:23 2007
    Info: Elapsed time: 00:00:02