dianzhen1.fit.summary

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Thu Jul 05 23:12:08 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : dianzhen1
Top-level Entity Name : dianzhen1
Family : MAX3000A
Device : EPM3128ATC100-10
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 44 / 128 ( 34 % )
Total pins : 21 / 80 ( 26 % )