clock6.v

通过VERILOG HDL语言使用CPLD连接PS2键盘

module clock6 (clk,lddat,ldsel);
input clk;
output [7:0] lddat;
output [5:0] ldsel;
reg [22:0] count;
reg [23:0] min;
reg [7:0] lddat_reg;
reg [3:0] ledbuf;
reg [5:0] ldsel_reg;
reg sec;
always @ (negedge clk)
	begin
	count=count+1;
	if(count==23'h74601e)
		begin
			count=23'h000000;
			sec=~sec;
		end
	end
always @ (count[12:10])
	begin
		case(count[12:10])
			3'b000:ledbuf=min[3:0];
			3'b001:ledbuf=min[7:4];
			3'b010:ledbuf=min[11:8];
			3'b011:ledbuf=min[15:12];
            3'b100:ledbuf=min[19:16];
            3'b101:ledbuf=min[23:20];
		endcase
	end

always	@ (ledbuf)
	begin
		case(ledbuf)
			4'h0: lddat_reg = 8'hc0;
			4'h1: lddat_reg = 8'hf9;				//显示1
			4'h2: lddat_reg = 8'ha4;				//显示2
			4'h3: lddat_reg = 8'hb0;				//显示3
			4'h4: lddat_reg = 8'h99;				//显示4
			4'h5: lddat_reg = 8'h92;				//显示5
			4'h6: lddat_reg = 8'h82;				//显示6
			4'h7: lddat_reg = 8'hf8;				//显示7
			4'h8: lddat_reg = 8'h80;				//显示8
			4'h9: lddat_reg = 8'h90;				//显示9      
		endcase
	end

always @ (count[12:10])
	begin
		case(count[12:10])
			3'b000:ldsel_reg=6'b100000;
			3'b001:ldsel_reg=6'b010000;
			3'b010:ldsel_reg=6'b001000;
			3'b011:ldsel_reg=6'b000100;
            3'b100:ldsel_reg=6'b000010;
            3'b101:ldsel_reg=6'b000001;
		endcase
	end

always @ (negedge sec)
		begin
			min[3:0]=min[3:0]+1;
			if(min[3:0]==4'ha)
				begin
					min[3:0]=4'h0;
					min[7:4]=min[7:4]+1;
					if(min[7:4]==4'h6)
						begin
							min[7:4]=4'h0;
							min[11:8]=min[11:8]+1;
							if(min[11:8]==4'ha)
								begin
									min[11:8]=4'h0;
									min[15:12]=min[15:12]+1;
									if(min[15:12]==4'h6) 
                                    begin
                                    min[15:12]=4'h0;
                                    min[19:16]=min[19:16]+1;
                                        if(min[19:16]==4'ha)
                                         begin
                                         min[19:16]=4'h0;
                                         min[23:20]=min[23:20]+1;
                                         if(min[23:20]==4'h6)
                                         min[23:20]=4'h0;                         
							           	end
						            end
				                end
		               end
               end
end
assign lddat=lddat_reg;
assign ldsel=ldsel_reg;	 
endmodule