led6.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 06 00:16:02 2007 " "Info: Processing started: Fri Jul 06 00:16:02 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led6 -c led6 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led6 -c led6" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led6.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file led6.v" { { "Info" "ISGN_ENTITY_NAME" "1 led6 " "Info: Found entity 1: led6" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led6 " "Info: Elaborating entity \"led6\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "led6.v(26) " "Warning: (10270) Verilog HDL statement warning at led6.v(26): incomplete Case Statement has no default case item" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "seg_reg led6.v(24) " "Warning: Verilog HDL Always Construct warning at led6.v(24): variable \"seg_reg\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"seg_reg\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 24 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 6 led6.v(47) " "Warning: Verilog HDL assignment warning at led6.v(47): truncated value with size 8 to match size of target (6)" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 47 0 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[0\] " "Warning: LATCH primitive \"seg_reg\[0\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[1\] " "Warning: LATCH primitive \"seg_reg\[1\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[2\] " "Warning: LATCH primitive \"seg_reg\[2\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[3\] " "Warning: LATCH primitive \"seg_reg\[3\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[4\] " "Warning: LATCH primitive \"seg_reg\[4\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[5\] " "Warning: LATCH primitive \"seg_reg\[5\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_USE_LATCH" "seg_reg\[6\] " "Warning: LATCH primitive \"seg_reg\[6\]\" is permanently enabled" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 5 -1 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~0 37 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=37) from the following logic: \"count\[0\]~0\"" {  } { { "led6.v" "count\[0\]~0" { Text "C:/altera/quartus50/six SMG/led6.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_constant.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_constant.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_constant " "Info: Found entity 1: lpm_constant" {  } { { "lpm_constant.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_constant.tdf" 35 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "28 " "Info: Ignored 28 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "28 " "Info: Ignored 28 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 2 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sl\[0\] VCC " "Warning: Pin \"sl\[0\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sl\[1\] VCC " "Warning: Pin \"sl\[1\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sl\[2\] VCC " "Warning: Pin \"sl\[2\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sl\[3\] VCC " "Warning: Pin \"sl\[3\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sl\[4\] VCC " "Warning: Pin \"sl\[4\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 3 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "sl\[5\] VCC " "Warning: Pin \"sl\[5\]\" stuck at VCC" {  } { { "led6.v" "" { Text "C:/altera/quartus50/six SMG/led6.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "57 " "Info: Implemented 57 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "42 " "Info: Implemented 42 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 06 00:16:08 2007 " "Info: Processing ended: Fri Jul 06 00:16:08 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}