fashe.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘

; cmpconst.inc                     ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal50.inc                    ; yes             ; Other                  ; c:/altera/quartus50/libraries/megafunctions/aglobal50.inc           ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------+


+--------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary            ;
+----------------------+---------------------------------+
; Resource             ; Usage                           ;
+----------------------+---------------------------------+
; Logic cells          ; 17                              ;
; Total registers      ; 17                              ;
; I/O pins             ; 2                               ;
; Maximum fan-out node ; lpm_counter:count_rtl_0|dffs[7] ;
; Maximum fan-out      ; 12                              ;
; Total fan-out        ; 140                             ;
; Average fan-out      ; 7.37                            ;
+----------------------+---------------------------------+


+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                               ;
+------------------------------+------------+------+--------------------------------+
; Compilation Hierarchy Node   ; Macrocells ; Pins ; Full Hierarchy Name            ;
+------------------------------+------------+------+--------------------------------+
; |fashe                       ; 17         ; 2    ; |fashe                         ;
;    |lpm_counter:count_rtl_0| ; 11         ; 0    ; |fashe|lpm_counter:count_rtl_0 ;
+------------------------------+------------+------+--------------------------------+


+--------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:count_rtl_0 ;
+------------------------+----------+--------------------------------------+
; Parameter Name         ; Value    ; Type                                 ;
+------------------------+----------+--------------------------------------+
; AUTO_CARRY_CHAINS      ; ON       ; AUTO_CARRY                           ;
; IGNORE_CARRY_BUFFERS   ; OFF      ; IGNORE_CARRY                         ;
; AUTO_CASCADE_CHAINS    ; ON       ; AUTO_CASCADE                         ;
; IGNORE_CASCADE_BUFFERS ; OFF      ; IGNORE_CASCADE                       ;
; LPM_WIDTH              ; 11       ; Untyped                              ;
; LPM_DIRECTION          ; UP       ; Untyped                              ;
; LPM_MODULUS            ; 0        ; Untyped                              ;
; LPM_AVALUE             ; UNUSED   ; Untyped                              ;
; LPM_SVALUE             ; UNUSED   ; Untyped                              ;
; DEVICE_FAMILY          ; MAX3000A ; Untyped                              ;
; CARRY_CHAIN            ; MANUAL   ; Untyped                              ;
; CARRY_CHAIN_LENGTH     ; 48       ; CARRY_CHAIN_LENGTH                   ;
; NOT_GATE_PUSH_BACK     ; ON       ; NOT_GATE_PUSH_BACK                   ;
; CARRY_CNT_EN           ; SMART    ; Untyped                              ;
; LABWIDE_SCLR           ; ON       ; Untyped                              ;
; USE_NEW_VERSION        ; TRUE     ; Untyped                              ;
; CBXI_PARAMETER         ; NOTHING  ; Untyped                              ;
+------------------------+----------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/uart_send/fashe.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Jul 06 00:20:44 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fashe -c fashe
Info: Found 1 design units, including 1 entities, in source file fashe.v
    Info: Found entity 1: fashe
Info: Elaborating entity "fashe" for the top level hierarchy
Warning: Verilog HDL assignment warning at fashe.v(15): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at fashe.v(16): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fashe.v(20): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at fashe.v(21): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fashe.v(28): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at fashe.v(30): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at fashe.v(34): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fashe.v(43): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at fashe.v(44): truncated value with size 32 to match size of target (1)
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: "count[0]~11"
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clock" to global clock signal
Info: Implemented 19 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 17 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Fri Jul 06 00:20:46 2007
    Info: Elapsed time: 00:00:03