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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L11 is bb[0]~37
A1L11_p1_out = reset & a[0];
A1L11_or_out = A1L11_p1_out;
A1L11 = A1L11_or_out;
--A1L21 is bb[1]~39
A1L21_p1_out = reset & a[1];
A1L21_or_out = A1L21_p1_out;
A1L21 = A1L21_or_out;
--A1L31 is bb[2]~41
A1L31_p1_out = reset & a[2];
A1L31_or_out = A1L31_p1_out;
A1L31 = A1L31_or_out;
--A1L41 is bb[3]~43
A1L41_p1_out = reset & a[3];
A1L41_or_out = A1L41_p1_out;
A1L41 = A1L41_or_out;
--a[0] is a[0]
--operation mode is input
a[0] = INPUT();
--a[1] is a[1]
--operation mode is input
a[1] = INPUT();
--a[2] is a[2]
--operation mode is input
a[2] = INPUT();
--a[3] is a[3]
--operation mode is input
a[3] = INPUT();
--reset is reset
--operation mode is input
reset = INPUT();
--b[0] is b[0]
--operation mode is output
b[0] = OUTPUT(A1L11);
--b[1] is b[1]
--operation mode is output
b[1] = OUTPUT(A1L21);
--b[2] is b[2]
--operation mode is output
b[2] = OUTPUT(A1L31);
--b[3] is b[3]
--operation mode is output
b[3] = OUTPUT(A1L41);
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