cpld-0832.vhd

来自「VHDL语言编写的DAC0832代码」· VHDL 代码 · 共 46 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dac is
	port(wr,cs:out std_logic;
	     clk:in std_logic;
	     c_state:out std_logic_vector(2 downto 0);
	     dout:out std_logic_vector(7 downto 0);
	     oe1,oe2,dir1,dir2:out std_logic);
end dac;

architecture one of dac is
signal fp:std_logic_vector(15 downto 0);
signal f:std_logic; 
signal send:std_logic_vector(7 downto 0);

begin
cs<='0';wr<='0';
dout<=send;
rega:process(clk)
	begin
	if (clk'event and clk='1') then
	if fp=1 then
	  fp<="0000000000000000";
       f<=not f;       
	else
		fp<=fp+1;				
	end if;
  end if;
end process rega;

reg:process(f)
 begin
  if (f'event and f='1') then send<=send+1;
  end if;  
end process reg;

 oe1<='0';
 dir1<='1';
 oe2<='0';
 dir2<='1';

end one；