cpld_dpd.map.qmsg

DVD数字伺服系统DPD循迹伺服相位比较算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 15 15:12:44 2008 " "Info: Processing started: Tue Apr 15 15:12:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpld_dpd -c cpld_dpd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpld_dpd -c cpld_dpd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../已有方案文档/软件资料/20061214版本/CPLD_DPD/dpd5.gdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../已有方案文档/软件资料/20061214版本/CPLD_DPD/dpd5.gdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpd5 " "Info: Found entity 1: dpd5" {  } { { "../../已有方案文档/软件资料/20061214版本/CPLD_DPD/dpd5.gdf" "" { Schematic "G:/软件开发/SHENZHEN（8.22）/QINGHUA_CHPAVC/项目文件/已有方案文档/软件资料/20061214版本/CPLD_DPD/dpd5.gdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"moudle\";  expecting \"module\", or \"macromodule\", or \"primitive\", or \"(*\", or \"config\", or \"include\", or \"library\" cpld_dpd.v(1) " "Error (10170): Verilog HDL syntax error at cpld_dpd.v(1) near text \"moudle\";  expecting \"module\", or \"macromodule\", or \"primitive\", or \"(*\", or \"config\", or \"include\", or \"library\"" {  } { { "cpld_dpd.v" "" { Text "G:/软件开发/SHENZHEN（8.22）/QINGHUA_CHPAVC/项目文件/设计文档/CPLD_DPD/cpld_dpd.v" 1 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld_dpd.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file cpld_dpd.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Apr 15 15:12:44 2008 " "Error: Processing ended: Tue Apr 15 15:12:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}