prev_cmp_generalboardub2.map.qmsg

飞机电气检测的界面程序设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:32:30 2007 " "Info: Processing started: Thu Dec 27 20:32:30 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off generalBoardUb2 -c generalBoardUb2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off generalBoardUb2 -c generalBoardUb2" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "generalBoardUb2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file generalBoardUb2.v" { { "Info" "ISGN_ENTITY_NAME" "1 generalBoardUb2 " "Info: Found entity 1: generalBoardUb2" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "generalBoardUb2 " "Info: Elaborating entity \"generalBoardUb2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 generalBoardUb2.v(23) " "Warning (10230): Verilog HDL assignment warning at generalBoardUb2.v(23): truncated value with size 32 to match size of target (6)" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 generalBoardUb2.v(24) " "Warning (10230): Verilog HDL assignment warning at generalBoardUb2.v(24): truncated value with size 32 to match size of target (6)" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 generalBoardUb2.v(25) " "Warning (10230): Verilog HDL assignment warning at generalBoardUb2.v(25): truncated value with size 32 to match size of target (6)" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addressA\[1\] " "Warning: No output dependent on input pin \"addressA\[1\]\"" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addressB\[1\] " "Warning: No output dependent on input pin \"addressB\[1\]\"" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addressC\[1\] " "Warning: No output dependent on input pin \"addressC\[1\]\"" {  } { { "generalBoardUb2.v" "" { Text "D:/CPLD GENERALBOARD/Ub2/generalBoardUb2.v" 7 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "60 " "Info: Implemented 60 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_MCELLS" "18 " "Info: Implemented 18 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_SEXPS" "10 " "Info: Implemented 10 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "129 " "Info: Allocated 129 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:32:33 2007 " "Info: Processing ended: Thu Dec 27 20:32:33 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}