📄 generalub1.pin
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCC : Dedicated power pin, which MUST be connected to VCC.
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
-- NON_MIGRATABLE: This pin cannot be migrated.
---------------------------------------------------------------------------------
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
CHIP "generalUb1" ASSIGNED TO AN: EPM7032SLC44-10
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
addressA[2] : 1 : input : TTL : : : Y
addressA[1] : 2 : input : TTL : : : Y
VCC : 3 : power : : : :
addressA[5] : 4 : input : TTL : : : Y
addressA[6] : 5 : input : TTL : : : Y
bse : 6 : input : TTL : : : Y
TDI : 7 : input : TTL : : : N
addressB[1] : 8 : input : TTL : : : Y
addressB[2] : 9 : input : TTL : : : Y
GND : 10 : gnd : : : :
addressB[3] : 11 : input : TTL : : : Y
addressB[4] : 12 : input : TTL : : : Y
TMS : 13 : input : TTL : : : N
addressB[5] : 14 : input : TTL : : : Y
VCC : 15 : power : : : :
addressB[6] : 16 : input : TTL : : : Y
addressC[1] : 17 : input : TTL : : : Y
addressC[2] : 18 : input : TTL : : : Y
addressC[3] : 19 : input : TTL : : : Y
addressC[4] : 20 : input : TTL : : : Y
addressC[5] : 21 : input : TTL : : : Y
GND : 22 : gnd : : : :
VCC : 23 : power : : : :
addressC[6] : 24 : input : TTL : : : Y
bte[3] : 25 : input : TTL : : : Y
bte[2] : 26 : input : TTL : : : Y
bte[1] : 27 : input : TTL : : : Y
kle[1] : 28 : output : TTL : : : Y
kle[2] : 29 : output : TTL : : : Y
GND : 30 : gnd : : : :
kle[3] : 31 : output : TTL : : : Y
TCK : 32 : input : TTL : : : N
kle[4] : 33 : output : TTL : : : Y
kle[5] : 34 : output : TTL : : : Y
VCC : 35 : power : : : :
kle[6] : 36 : output : TTL : : : Y
kle[7] : 37 : output : TTL : : : Y
TDO : 38 : output : TTL : : : N
kle[8] : 39 : output : TTL : : : Y
kle[9] : 40 : output : TTL : : : Y
kle[10] : 41 : output : TTL : : : Y
GND : 42 : gnd : : : :
addressA[4] : 43 : input : TTL : : : Y
addressA[3] : 44 : input : TTL : : : Y
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