generalub1.vo

飞机电气检测的界面程序设计

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

// DATE "12/27/2007 20:50:41"

// 
// Device: Altera EPM7032SLC44-10 Package PLCC44
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module generalUb1 (
	bse,
	bte,
	addressA,
	addressB,
	addressC,
	kle);
input 	bse;
input 	[3:1] bte;
input 	[6:1] addressA;
input 	[6:1] addressB;
input 	[6:1] addressC;
output 	[10:1] kle;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("generalUb1_v.sdo");
// synopsys translate_on

wire \bse~dataout ;
wire \kle~3294_dataout ;
wire \kle~3295_dataout ;
wire \kle~3299_dataout ;
wire \kle~3300_dataout ;
wire \kle~3301_dataout ;
wire \kle~3305_dataout ;
wire \kle~3306_dataout ;
wire \kle~3312_dataout ;
wire \kle~3318_dataout ;
wire \kle~3319_dataout ;
wire \kle~3320_dataout ;
wire \kle~3321_dataout ;
wire \kle~3327_dataout ;
wire \kle~3329_dataout ;
wire \kle~3335_dataout ;
wire \kle~3342_dataout ;
wire \kle~3348_dataout ;
wire \kle~3349_dataout ;
wire \kle~3350_dataout ;
wire \kle~3356_dataout ;
wire [6:1] \addressA~dataout ;
wire [6:1] \addressB~dataout ;
wire [6:1] \addressC~dataout ;
wire [3:1] \bte~dataout ;


// atom is at PIN_1
max_io \addressA[2]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressA~dataout [2]),
	.padio(addressA[2]));
// synopsys translate_off
defparam \addressA[2]~I .bus_hold = "false";
defparam \addressA[2]~I .open_drain_output = "false";
defparam \addressA[2]~I .operation_mode = "input";
defparam \addressA[2]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_44
max_io \addressA[3]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressA~dataout [3]),
	.padio(addressA[3]));
// synopsys translate_off
defparam \addressA[3]~I .bus_hold = "false";
defparam \addressA[3]~I .open_drain_output = "false";
defparam \addressA[3]~I .operation_mode = "input";
defparam \addressA[3]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_43
max_io \addressA[4]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressA~dataout [4]),
	.padio(addressA[4]));
// synopsys translate_off
defparam \addressA[4]~I .bus_hold = "false";
defparam \addressA[4]~I .open_drain_output = "false";
defparam \addressA[4]~I .operation_mode = "input";
defparam \addressA[4]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_4
max_io \addressA[5]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressA~dataout [5]),
	.padio(addressA[5]));
// synopsys translate_off
defparam \addressA[5]~I .bus_hold = "false";
defparam \addressA[5]~I .open_drain_output = "false";
defparam \addressA[5]~I .operation_mode = "input";
defparam \addressA[5]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_6
max_io \bse~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\bse~dataout ),
	.padio(bse));
// synopsys translate_off
defparam \bse~I .bus_hold = "false";
defparam \bse~I .open_drain_output = "false";
defparam \bse~I .operation_mode = "input";
defparam \bse~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_5
max_io \addressA[6]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressA~dataout [6]),
	.padio(addressA[6]));
// synopsys translate_off
defparam \addressA[6]~I .bus_hold = "false";
defparam \addressA[6]~I .open_drain_output = "false";
defparam \addressA[6]~I .operation_mode = "input";
defparam \addressA[6]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_16
max_io \addressB[6]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressB~dataout [6]),
	.padio(addressB[6]));
// synopsys translate_off
defparam \addressB[6]~I .bus_hold = "false";
defparam \addressB[6]~I .open_drain_output = "false";
defparam \addressB[6]~I .operation_mode = "input";
defparam \addressB[6]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_14
max_io \addressB[5]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressB~dataout [5]),
	.padio(addressB[5]));
// synopsys translate_off
defparam \addressB[5]~I .bus_hold = "false";
defparam \addressB[5]~I .open_drain_output = "false";
defparam \addressB[5]~I .operation_mode = "input";
defparam \addressB[5]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_9
max_io \addressB[2]~I (
	.datain(gnd),
	.oe(gnd),
	.dataout(\addressB~dataout [2]),
	.padio(addressB[2]));
// synopsys translate_off
defparam \addressB[2]~I .bus_hold = "false";
defparam \addressB[2]~I .open_drain_output = "false";
defparam \addressB[2]~I .operation_mode = "input";
defparam \addressB[2]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_11
max_io \addressB[3]~I (
	.datain(gnd),
	.oe(gnd),