prev_cmp_generalub1.qmsg

来自「飞机电气检测的界面程序设计」· QMSG 代码 · 共 27 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:49:56 2007 " "Info: Processing started: Thu Dec 27 20:49:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off generalUb1 -c generalUb1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off generalUb1 -c generalUb1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "generalUb1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file generalUb1.v" { { "Info" "ISGN_ENTITY_NAME" "1 generalUb1 " "Info: Found entity 1: generalUb1" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "generalUb1 " "Info: Elaborating entity \"generalUb1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 generalUb1.v(23) " "Warning (10230): Verilog HDL assignment warning at generalUb1.v(23): truncated value with size 32 to match size of target (6)" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 generalUb1.v(24) " "Warning (10230): Verilog HDL assignment warning at generalUb1.v(24): truncated value with size 32 to match size of target (6)" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 generalUb1.v(25) " "Warning (10230): Verilog HDL assignment warning at generalUb1.v(25): truncated value with size 32 to match size of target (6)" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addressA\[1\] " "Warning: No output dependent on input pin \"addressA\[1\]\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addressB\[1\] " "Warning: No output dependent on input pin \"addressB\[1\]\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 6 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addressC\[1\] " "Warning: No output dependent on input pin \"addressC\[1\]\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 7 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "61 " "Info: Implemented 61 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_MCELLS" "27 " "Info: Implemented 27 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Info: Implemented 2 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "129 " "Info: Allocated 129 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:49:59 2007 " "Info: Processing ended: Thu Dec 27 20:49:59 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:50:00 2007 " "Info: Processing started: Thu Dec 27 20:50:00 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off generalUb1 -c generalUb1 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off generalUb1 -c generalUb1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "generalUb1 EPM7032SLC44-10 " "Info: Selected device EPM7032SLC44-10 for design \"generalUb1\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3288 " "Warning: Macrocell buffer inserted after node \"kle~3288\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3294 " "Warning: Macrocell buffer inserted after node \"kle~3294\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3301 " "Warning: Macrocell buffer inserted after node \"kle~3301\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3307 " "Warning: Macrocell buffer inserted after node \"kle~3307\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3316 " "Warning: Macrocell buffer inserted after node \"kle~3316\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3324 " "Warning: Macrocell buffer inserted after node \"kle~3324\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WF7K_LCELL_INSERTED" "kle~3331 " "Warning: Macrocell buffer inserted after node \"kle~3331\"" {  } { { "generalUb1.v" "" { Text "D:/CPLD GENERALBOARD/Ub1/generalUb1.v" 9 -1 0 } }  } 0 0 "Macrocell buffer inserted after node \"%1!s!\"" 0 0 "" 0}
{ "Error" "EF7K_PROJ_TOO_MANY_MCELL" "33 32 " "Error: Design requires 33 macrocells, but the selected device can contain only 32 macrocells" {  } {  } 0 0 "Design requires %1!d! macrocells, but the selected device can contain only %2!d! macrocells" 0 0 "" 0}
{ "Error" "EF7K_FIT_FAIL" "" "Error: Can't find fit" {  } {  } 0 0 "Can't find fit" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Fitter 2 s 7 s Quartus II " "Error: Quartus II Fitter was unsuccessful. 2 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Dec 27 20:50:01 2007 " "Error: Processing ended: Thu Dec 27 20:50:01 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 2 s 14 s " "Error: Quartus II Full Compilation was unsuccessful. 2 errors, 14 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}