generalub1.v

来自「飞机电气检测的界面程序设计」· Verilog 代码 · 共 54 行

module generalUb1(bse,bte,addressA,addressB,addressC,kle);
//input
input bse;
input[3:1] bte;
input[6:1] addressA;
input[6:1] addressB;
input[6:1] addressC;
//output
output[10:1] kle;

reg[10:1] kle;
reg[32:1] tmp;
reg[6:1] a;
reg[6:1] b;
reg[6:1] c;
reg[32:1] allA;
reg[32:1] allB;
reg[32:1] allC;


always @(bse or bte or addressA or addressB or addressC)	   
   begin
		a=(addressA>>1)+1;
		b=(addressB>>1)+1;
		c=(addressC>>1)+1;
	    kle=10'b0;
	    tmp=32'b0;
	    allA=32'b11111111111111111111111111111111>>(32-c);
	    allB=32'b11111111111111111111111111111111<<(b-1);
	    allC=32'b0;
	
		if(bse==1)	
		   begin
		       allC[a]=1'b1;
		       tmp=allC;
		       kle=allC[10:1];
		   end
		else
			     kle=10'b0; 
        if(bte==4)
		   begin 
	            allC=allA&allB;//|tmp;
	            kle=allC[10:1]|tmp[10:1];
	       end
	    else if(bte==5)
			    kle=allB[10:1]|tmp[10:1];
	   	else if(bte==6)
	           kle=allA[10:1]|tmp[10:1];
		else if(bte==7)
		      kle=10'b1111111111;
		else
		      kle=10'b0|tmp[10:1];
	end	
endmodule