generalboardub2.vo

飞机电气检测的界面程序设计

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

// DATE "12/27/2007 21:14:55"

// 
// Device: Altera EPM7032SLC44-10 Package PLCC44
// 

// 
// This Verilog file should be used for PrimeTime (Verilog) only
// 

`timescale 1 ps/ 1 ps

module generalBoardUb2 (
	bse,
	bte,
	addressA,
	addressB,
	addressC,
	kle);
input 	bse;
input 	[3:1] bte;
input 	[6:1] addressA;
input 	[6:1] addressB;
input 	[6:1] addressC;
output 	[10:1] kle;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("generalBoardUb2_v.sdo");
// synopsys translate_on

wire \addressA[2]~dataout ;
wire \addressA[3]~dataout ;
wire \addressA[4]~dataout ;
wire \addressA[5]~dataout ;
wire \bse~dataout ;
wire \addressA[6]~dataout ;
wire \addressB[5]~dataout ;
wire \addressB[6]~dataout ;
wire \bte[2]~dataout ;
wire \kle~3713bal_dataout ;
wire \bte[1]~dataout ;
wire \bte[3]~dataout ;
wire \addressB[2]~dataout ;
wire \addressB[3]~dataout ;
wire \kle~3714bal_dataout ;
wire \addressB[4]~dataout ;
wire \addressC[4]~dataout ;
wire \addressC[3]~dataout ;
wire \kle~3715bal_dataout ;
wire \addressC[5]~dataout ;
wire \addressC[6]~dataout ;
wire \kle~3721_dataout ;
wire \kle~3722_dataout ;
wire \kle~3723_dataout ;
wire \kle~3729_dataout ;
wire \kle~3731_dataout ;
wire \kle~3732_dataout ;
wire \kle~3738_dataout ;
wire \kle~3746_dataout ;
wire \kle~3748_dataout ;
wire \kle~3754_dataout ;
wire \kle~3755_dataout ;
wire \addressC[2]~dataout ;
wire \kle~3760_dataout ;
wire \kle~3767_dataout ;
wire \kle~3768_dataout ;
wire \kle~3769_dataout ;
wire \kle~3773_dataout ;
wire \kle~3780_dataout ;
wire \kle~3775sexpand0_dataout ;
wire \kle~3782_dataout ;
wire \kle~3790_dataout ;

wire \ALT_INV_bte[1]~dataout ;
wire \ALT_INV_bte[2]~dataout ;
wire \ALT_INV_bte[3]~dataout ;
wire \ALT_INV_addressA[2]~dataout ;
wire \ALT_INV_addressA[3]~dataout ;
wire \ALT_INV_addressA[4]~dataout ;
wire \ALT_INV_addressA[5]~dataout ;
wire \ALT_INV_addressB[2]~dataout ;
wire \ALT_INV_addressB[3]~dataout ;
wire \ALT_INV_addressB[4]~dataout ;
wire \ALT_INV_addressC[2]~dataout ;
wire \ALT_INV_addressC[3]~dataout ;
wire \ALT_INV_addressC[4]~dataout ;
wire \ALT_INV_addressC[5]~dataout ;
wire \ALT_INV_addressC[6]~dataout ;

INV \INV_INST_bte[1]~dataout  (
	.IN1(\bte[1]~dataout ),
	.Y(\ALT_INV_bte[1]~dataout ));

INV \INV_INST_bte[2]~dataout  (
	.IN1(\bte[2]~dataout ),
	.Y(\ALT_INV_bte[2]~dataout ));

INV \INV_INST_bte[3]~dataout  (
	.IN1(\bte[3]~dataout ),
	.Y(\ALT_INV_bte[3]~dataout ));

INV \INV_INST_addressA[2]~dataout  (
	.IN1(\addressA[2]~dataout ),
	.Y(\ALT_INV_addressA[2]~dataout ));

INV \INV_INST_addressA[3]~dataout  (
	.IN1(\addressA[3]~dataout ),
	.Y(\ALT_INV_addressA[3]~dataout ));

INV \INV_INST_addressA[4]~dataout  (
	.IN1(\addressA[4]~dataout ),
	.Y(\ALT_INV_addressA[4]~dataout ));

INV \INV_INST_addressA[5]~dataout  (
	.IN1(\addressA[5]~dataout ),
	.Y(\ALT_INV_addressA[5]~dataout ));

INV \INV_INST_addressB[2]~dataout  (
	.IN1(\addressB[2]~dataout ),
	.Y(\ALT_INV_addressB[2]~dataout ));

INV \INV_INST_addressB[3]~dataout  (
	.IN1(\addressB[3]~dataout ),
	.Y(\ALT_INV_addressB[3]~dataout ));

INV \INV_INST_addressB[4]~dataout  (
	.IN1(\addressB[4]~dataout ),
	.Y(\ALT_INV_addressB[4]~dataout ));

INV \INV_INST_addressC[2]~dataout  (
	.IN1(\addressC[2]~dataout ),
	.Y(\ALT_INV_addressC[2]~dataout ));

INV \INV_INST_addressC[3]~dataout  (
	.IN1(\addressC[3]~dataout ),
	.Y(\ALT_INV_addressC[3]~dataout ));

INV \INV_INST_addressC[4]~dataout  (
	.IN1(\addressC[4]~dataout ),
	.Y(\ALT_INV_addressC[4]~dataout ));

INV \INV_INST_addressC[5]~dataout  (
	.IN1(\addressC[5]~dataout ),
	.Y(\ALT_INV_addressC[5]~dataout ));

INV \INV_INST_addressC[6]~dataout  (
	.IN1(\addressC[6]~dataout ),
	.Y(\ALT_INV_addressC[6]~dataout ));

// atom is at PIN_1
max_io \addressA[2]~I (
	.datain(gnd),
	.oe(gnd),
	.modesel(9'b101010001),
	.dataout(\addressA[2]~dataout ),
	.padio(addressA[2]));
// synopsys translate_off
// defparam \addressA[2]~I .bus_hold = "false";
// defparam \addressA[2]~I .open_drain_output = "false";
// defparam \addressA[2]~I .operation_mode = "input";
// defparam \addressA[2]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_44
max_io \addressA[3]~I (
	.datain(gnd),
	.oe(gnd),
	.modesel(9'b101010001),
	.dataout(\addressA[3]~dataout ),
	.padio(addressA[3]));
// synopsys translate_off
// defparam \addressA[3]~I .bus_hold = "false";
// defparam \addressA[3]~I .open_drain_output = "false";
// defparam \addressA[3]~I .operation_mode = "input";
// defparam \addressA[3]~I .weak_pull_up = "false";
// synopsys translate_on

// atom is at PIN_43
max_io \addressA[4]~I (
	.datain(gnd),
	.oe(gnd),
	.modesel(9'b101010001),
	.dataout(\addressA[4]~dataout ),
	.padio(addressA[4]));
// synopsys translate_off
// defparam \addressA[4]~I .bus_hold = "false";
// defparam \addressA[4]~I .open_drain_output = "false";
// defparam \addressA[4]~I .operation_mode = "input";
// defparam \addressA[4]~I .weak_pull_up = "false";