generalboardub3.tan.qmsg

飞机电气检测的界面程序设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:19:46 2007 " "Info: Processing started: Thu Dec 27 20:19:46 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "bte\[3\] kle\[1\] 19.600 ns Longest " "Info: Longest tpd from source pin \"bte\[3\]\" to destination pin \"kle\[1\]\" is 19.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns bte\[3\] 1 PIN PIN_25 15 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_25; Fanout = 15; PIN Node = 'bte\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { bte[3] } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns kle~493 2 COMB LC29 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC29; Fanout = 1; COMB Node = 'kle~493'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { bte[3] kle~493 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 7.300 ns kle~492 3 COMB LC30 1 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 7.300 ns; Loc. = LC30; Fanout = 1; COMB Node = 'kle~492'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { kle~493 kle~492 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 10.100 ns kle~481 4 COMB LC31 1 " "Info: 4: + IC(0.000 ns) + CELL(2.800 ns) = 10.100 ns; Loc. = LC31; Fanout = 1; COMB Node = 'kle~481'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { kle~492 kle~481 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 18.100 ns kle~494 5 COMB LC28 1 " "Info: 5: + IC(1.000 ns) + CELL(7.000 ns) = 18.100 ns; Loc. = LC28; Fanout = 1; COMB Node = 'kle~494'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { kle~481 kle~494 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 19.600 ns kle\[1\] 6 PIN PIN_28 0 " "Info: 6: + IC(0.000 ns) + CELL(1.500 ns) = 19.600 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'kle\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { kle~494 kle[1] } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.600 ns ( 89.80 % ) " "Info: Total cell delay = 17.600 ns ( 89.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 10.20 % ) " "Info: Total interconnect delay = 2.000 ns ( 10.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "19.600 ns" { bte[3] kle~493 kle~492 kle~481 kle~494 kle[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "19.600 ns" { bte[3] bte[3]~out kle~493 kle~492 kle~481 kle~494 kle[1] } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns 1.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 0.800ns 2.800ns 7.000ns 1.500ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:19:47 2007 " "Info: Processing ended: Thu Dec 27 20:19:47 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}