📄 prev_cmp_generalboardub3.qmsg
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:14:26 2007 " "Info: Processing ended: Thu Dec 27 20:14:26 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:14:27 2007 " "Info: Processing started: Thu Dec 27 20:14:27 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3 " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:14:31 2007 " "Info: Processing ended: Thu Dec 27 20:14:31 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:14:32 2007 " "Info: Processing started: Thu Dec 27 20:14:32 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" { } { } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "bte\[3\] kle\[1\] 11.600 ns Longest " "Info: Longest tpd from source pin \"bte\[3\]\" to destination pin \"kle\[1\]\" is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns bte\[3\] 1 PIN PIN_5 15 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_5; Fanout = 15; PIN Node = 'bte\[3\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { bte[3] } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns kle~483 2 COMB LC1 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC1; Fanout = 1; COMB Node = 'kle~483'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { bte[3] kle~483 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 7.300 ns kle~487 3 COMB LC2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 7.300 ns; Loc. = LC2; Fanout = 1; COMB Node = 'kle~487'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { kle~483 kle~487 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 10.100 ns kle~482 4 COMB LC3 1 " "Info: 4: + IC(0.000 ns) + CELL(2.800 ns) = 10.100 ns; Loc. = LC3; Fanout = 1; COMB Node = 'kle~482'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { kle~487 kle~482 } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 11.600 ns kle\[1\] 5 PIN PIN_6 0 " "Info: 5: + IC(0.000 ns) + CELL(1.500 ns) = 11.600 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'kle\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { kle~482 kle[1] } "NODE_NAME" } } { "generalBoardUb3.v" "" { Text "D:/CPLD GENERALBOARD/Ub3/generalBoardUb3.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.600 ns ( 91.38 % ) " "Info: Total cell delay = 10.600 ns ( 91.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 8.62 % ) " "Info: Total interconnect delay = 1.000 ns ( 8.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { bte[3] kle~483 kle~487 kle~482 kle[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { bte[3] bte[3]~out kle~483 kle~487 kle~482 kle[1] } { 0.000ns 0.000ns 1.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.500ns 5.000ns 0.800ns 2.800ns 1.500ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:14:33 2007 " "Info: Processing ended: Thu Dec 27 20:14:33 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 20:14:34 2007 " "Info: Processing started: Thu Dec 27 20:14:34 2007" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3 " "Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "generalBoardUb3.vo generalBoardUb3_v.sdo D:/CPLD GENERALBOARD/Ub3/simulation/activehdl/ simulation " "Info: Generated files \"generalBoardUb3.vo\" and \"generalBoardUb3_v.sdo\" in directory \"D:/CPLD GENERALBOARD/Ub3/simulation/activehdl/\" for EDA simulation tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0}
{ "Info" "IWSC_DONE_HDL_SDO_GENERATION" "generalBoardUb3.vo generalBoardUb3_v.sdo D:/CPLD GENERALBOARD/Ub3/timing/primetime/ timing analysis " "Info: Generated files \"generalBoardUb3.vo\" and \"generalBoardUb3_v.sdo\" in directory \"D:/CPLD GENERALBOARD/Ub3/timing/primetime/\" for EDA timing analysis tool" { } { } 0 0 "Generated files \"%1!s!\" and \"%2!s!\" in directory \"%3!s!\" for EDA %4!s! tool" 0 0 "" 0}
{ "Warning" "WPTO_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF" { } { } 0 0 "Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF" 0 0 "" 0}
{ "Info" "IPTO_FILE_GENERATED_MSG" "PrimeTime Tcl script file D:/CPLD GENERALBOARD/Ub3/timing/primetime/generalBoardUb3_pt_v.tcl " "Info: Generated PrimeTime Tcl script file D:/CPLD GENERALBOARD/Ub3/timing/primetime/generalBoardUb3_pt_v.tcl" { } { } 0 0 "Generated %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus II " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "99 " "Info: Allocated 99 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 20:14:35 2007 " "Info: Processing ended: Thu Dec 27 20:14:35 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 11 s " "Info: Quartus II Full Compilation was successful. 0 errors, 11 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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