📄 generalboardub3.fit.rpt
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; 32 ; 31 ; -- ; TCK ; input ; TTL ; ; N ;
; 33 ; 32 ; -- ; ke[2] ; output ; TTL ; ; Y ;
; 34 ; 33 ; -- ; ke[3] ; output ; TTL ; ; Y ;
; 35 ; 34 ; -- ; VCC ; power ; ; ; ;
; 36 ; 35 ; -- ; ke[4] ; output ; TTL ; ; Y ;
; 37 ; 36 ; -- ; ke[5] ; output ; TTL ; ; Y ;
; 38 ; 37 ; -- ; TDO ; output ; TTL ; ; N ;
; 39 ; 38 ; -- ; ke[6] ; output ; TTL ; ; Y ;
; 40 ; 39 ; -- ; ke[7] ; output ; TTL ; ; Y ;
; 41 ; 40 ; -- ; targetLed ; output ; TTL ; ; Y ;
; 42 ; 41 ; -- ; GND ; gnd ; ; ; ;
; 43 ; 42 ; -- ; addressA[4] ; input ; TTL ; ; Y ;
; 44 ; 43 ; -- ; addressA[3] ; input ; TTL ; ; Y ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
+--------------------------------------------------------------------------------------------------+
; I/O Standard ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; I/O Standard ; Input Vref ; Dedicated Input Pins ; Pins in I/O Bank1 ; Pins in I/O Bank2 ; Total ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
; TTL ; - ; 4 ; 0 ; 0 ; 4 ;
+--------------+------------+----------------------+-------------------+-------------------+-------+
+---------------------------------------------------------------------------+
; Dedicated Inputs I/O ;
+-------------+-------+-------+-------+--------------+------------+---------+
; Name ; Pin # ; Type ; VCCIO ; I/O Standard ; Input Vref ; Current ;
+-------------+-------+-------+-------+--------------+------------+---------+
; addressA[1] ; 2 ; Input ; -- ; TTL ; - ; 0 mA ;
; addressA[2] ; 1 ; Input ; -- ; TTL ; - ; 0 mA ;
; addressA[3] ; 44 ; Input ; -- ; TTL ; - ; 0 mA ;
; addressA[4] ; 43 ; Input ; -- ; TTL ; - ; 0 mA ;
+-------------+-------+-------+-------+--------------+------------+---------+
+-----------------------------------------------+
; Output Pin Default Load For Reported TCO ;
+--------------+-------+------------------------+
; I/O Standard ; Load ; Termination Resistance ;
+--------------+-------+------------------------+
; TTL ; 10 pF ; Not Available ;
+--------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+-------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |generalBoardUb3 ; 13 ; 36 ; |generalBoardUb3 ; work ;
+----------------------------+------------+------+---------------------+--------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------+-------------------+
; Name ; Fan-Out ;
+-------------+-------------------+
; addressA[6] ; 9 ;
; addressA[5] ; 9 ;
; addressA[4] ; 9 ;
; addressA[3] ; 9 ;
; addressA[2] ; 9 ;
; bse ; 9 ;
; bte[3] ; 5 ;
; addressC[6] ; 4 ;
; addressC[5] ; 4 ;
; addressC[4] ; 4 ;
; addressC[3] ; 4 ;
; bte[1] ; 3 ;
; addressB[6] ; 2 ;
; addressB[5] ; 2 ;
; addressB[4] ; 2 ;
; addressB[3] ; 2 ;
; addressB[2] ; 2 ;
; kle~494 ; 1 ;
; addressC[2] ; 1 ;
; bte[2] ; 1 ;
; kle~493 ; 1 ;
; kle~492 ; 1 ;
; kle~481 ; 1 ;
; kle~476 ; 1 ;
; ke~73 ; 1 ;
; ke~71 ; 1 ;
; tmp[32]~37 ; 1 ;
; tmp[31]~35 ; 1 ;
; ke~69 ; 1 ;
; ke~67 ; 1 ;
; ke~65 ; 1 ;
; bte[3]~10 ; 1 ;
+-------------+-------------------+
+-----------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 20 / 72 ( 28 % ) ;
+----------------------------+------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 6.50) ; Number of LABs (Total = 1) ;
+----------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
+--------------------------+------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+
; B ; LC17 ; bte[3] ; targetLed ;
; B ; LC24 ; addressA[2], bse, addressA[6], addressA[5], addressA[3], addressA[4] ; ke[2] ;
; B ; LC26 ; addressA[3], addressA[4], addressA[2], bse, addressA[6], addressA[5] ; ke[1] ;
; B ; LC23 ; addressA[2], bse, addressA[6], addressA[5], addressA[3], addressA[4] ; ke[3] ;
; B ; LC19 ; addressA[3], addressA[2], addressA[4], bse, addressA[6], addressA[5] ; ke[6] ;
; B ; LC18 ; addressA[3], addressA[2], addressA[4], bse, addressA[6], addressA[5] ; ke[7] ;
; B ; LC22 ; addressA[3], addressA[2], addressA[4], bse, addressA[6], addressA[5] ; ke[4] ;
; B ; LC21 ; addressA[3], addressA[2], addressA[4], bse, addressA[6], addressA[5] ; ke[5] ;
; B ; LC27 ; addressA[3], addressA[2], addressA[4], bse, addressA[6], addressA[5], bte[1], bte[3], addressC[3], addressC[2], addressC[6], addressC[5], addressC[4] ; kle[2] ;
; B ; LC31 ; kle~492, addressA[3], addressA[2], addressA[4], bse, addressA[6], addressA[5], bte[2], bte[1], bte[3], addressC[3], addressC[6], addressC[5], addressC[4], addressB[2], addressB[6] ; kle~494 ;
; B ; LC30 ; kle~493, addressB[5], bte[1], bte[3], addressB[4], addressB[3], addressB[2], addressC[3], addressC[6], addressC[5], addressC[4], addressB[6] ; kle~481 ;
; B ; LC29 ; addressB[5], bte[3], addressC[3], addressC[6], addressC[5], addressC[4], addressB[4], addressB[3] ; kle~492 ;
; B ; LC28 ; kle~481 ; kle[1] ;
+-----+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Thu Dec 27 20:19:39 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off generalBoardUb3 -c generalBoardUb3
Info: Selected device EPM7032SLC44-10 for design "generalBoardUb3"
Warning: Macrocell buffer inserted after node "kle~481"
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Allocated 137 megabytes of memory during processing
Info: Processing ended: Thu Dec 27 20:19:40 2007
Info: Elapsed time: 00:00:01
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