genralua.qsf

飞机电气检测的界面程序设计

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		genralUa_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE "EPM7032SLC44-10"
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY genralUa
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:01:37  DECEMBER 20, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_timing_analysis
set_global_assignment -name VERILOG_FILE genralUa.v
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_location_assignment PIN_5 -to address[6]
set_location_assignment PIN_4 -to address[5]
set_location_assignment PIN_43 -to address[4]
set_location_assignment PIN_44 -to address[3]
set_location_assignment PIN_1 -to address[2]
set_location_assignment PIN_2 -to address[1]
set_location_assignment PIN_6 -to bse
set_location_assignment PIN_41 -to ke[25]
set_location_assignment PIN_40 -to ke[24]
set_location_assignment PIN_39 -to ke[23]
set_location_assignment PIN_37 -to ke[22]
set_location_assignment PIN_36 -to ke[21]
set_location_assignment PIN_34 -to ke[20]
set_location_assignment PIN_33 -to ke[19]
set_location_assignment PIN_31 -to ke[18]
set_location_assignment PIN_29 -to ke[17]
set_location_assignment PIN_28 -to ke[16]
set_location_assignment PIN_27 -to ke[15]
set_location_assignment PIN_26 -to ke[14]
set_location_assignment PIN_25 -to ke[13]
set_location_assignment PIN_24 -to ke[12]
set_location_assignment PIN_21 -to ke[11]
set_location_assignment PIN_20 -to ke[10]
set_location_assignment PIN_19 -to ke[9]
set_location_assignment PIN_18 -to ke[8]
set_location_assignment PIN_17 -to ke[7]
set_location_assignment PIN_16 -to ke[6]
set_location_assignment PIN_14 -to ke[5]
set_location_assignment PIN_12 -to ke[4]
set_location_assignment PIN_11 -to ke[3]
set_location_assignment PIN_9 -to ke[2]
set_location_assignment PIN_8 -to ke[1]