fifo_fpga_1280x8.v

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

// fifo_fpga_1280X8.v
// fpga_core.v
///////////////////////////////////////////////////////////////////////////////////
// pc_camera project 
//funtion  FIFO 
//syscan  RD  :zhouhuaguo  
//mail :       [e-mail]
//acter--A3pro060   ,libero 8.0
///////////////////////////////////////////////////////////////////////////////////

`timescale  1ns/100ps

module fpga_core 
(
  
   clk_54,              //cmos  work clk  54Mhz;
   clk_48,              //usb IC work clk 48Mhz;
   data_out,            //16bit output data  from FIFO;
   datain,              //cmos  output data;
   RESET,               //fpga  reset ,active is high;
   frame_valid ,        //frame picture is valid;active is high
   line_valid,          //line data  is valid;active is high
   usb_flag,            //fifo in 68013a  is full or empty?
   reset ,               //FIFO in fpga ,active is high;  

   );


//input :
    
    input           RESET;
    input           reset;
    input           frame_valid;    
    input           line_valid;
    input           usb_flag;
    input           clk_48;
    input           clk_54;  
    input   [7:0]   datain; 


//output:

	output  [15:0]   data_out;


//wire:
    
	wire	[15:0]   dataout; 
    wire    [15:0]   data_out; 

    wire                full;   //write  data to FIFO is full or not;
    wire               empty;  //read data from FIFO is over or  not ;

 
 //reg :

    reg     [10:0]  count_w;
    reg     [9:0]   count_r;
  
    wire    [7:0]   cmos_data;
    reg             wen;            //we  fifo in fpga
    reg             ren;            //re  fifo in fpga

    reg     ctrl0;
    reg     ctrl1;      //next_state <= clear;
    reg     ctrl2;      //next_state <= idle;
    reg     ctrl3;      //next_state <= write;
    reg     ctrl4;      //next_state <= wirte_and_read ;
    reg     ctrl5;      //next_state <= write_clear;
    reg     ctrl6;


    reg     [4:0]   state;
    reg     [4:0]   next_state;
     
    
 //parament: 

    parameter   idle        =   5'b00001,    //FIFO is empty;
                start       =   5'b10001,
                write       =   5'b00010,    //move data to fifo;
                W_and_R     =   5'b00100,    //clear fifo data  and  read data to 68013a;
                write_c     =   5'b01000,    // only clear  FIFO data==0;
                clear       =   5'b00000,    //clear is over;
                clear_start =   5'b01001;

assign  data_out = (ren ==0)? dataout :16'hzzzz;
assign  cmos_data = ((line_valid==1'b1)&& (frame_valid==1'b1)&&(wen ==1'b0))? datain :8'h00;

 fifo_fpga1280x8 fifo_data_inst
    (
        .DATA   ( cmos_data  ),
        .DATAOUT( dataout   ),
        .WE     (   wen      ),
        .RE     (  ren       ),
        .WCLOCK ( clk_54     ),
        .RCLOCK ( clk_48     ),
        .FULL   ( full       ),
        .EMPTY  ( empty      ),
        .RESET  ( reset      )
        );


  always @( posedge clk_54 or negedge RESET)
    if ( RESET== 1'b0 )      
        state       =   5'b00;        
    else if (reset ==1'b0)           
        state       =   5'b00; 
    else state = next_state;

/////////////////////////////////////////////
//                                          //
//辨别line_valid的上沿;                     //
//                                          //
/////////////////////////////////////////////

    reg line_valid_1;
    reg line_valid_2;

always @(posedge clk_54 or negedge RESET )
    if (RESET== 1'b0 )
        begin 
        line_valid_1 <=0;
        line_valid_2 <=0;
        end 
     else
        begin
        line_valid_1 <= line_valid;
        line_valid_2 <= line_valid_1;
        end

/////////////////////////////////////////////
//                                          //
//辨别frame_valid的上沿;                     //
//                                          //
/////////////////////////////////////////////

    reg frame_valid_1;
    reg frame_valid_2;

always @(posedge clk_54 or negedge RESET )
    if (RESET== 1'b0 )
        begin 
        frame_valid_1 <=1'b0;
        frame_valid_2 <=1'b0;
        end 
     else
        begin
        frame_valid_1 <= frame_valid;
        frame_valid_2 <= frame_valid_1;
        end


  always @(posedge clk_54 or negedge RESET )
    if (RESET== 1'b0 )
        begin    
        wen = 1'b1; 
        ctrl0 = 1'b0;
        ctrl1 = 1'b0;
        ctrl4 = 1'b0;
        ctrl6 = 1'b0;     
        ctrl2 = 1'b0;
        ctrl3 = 1'b0;      
        ctrl5 = 1'b0;       
        count_w = 11'h000;       
        end
    else if(reset ==1'b0)
            begin           
            wen = 1'b1;           
            ctrl2 = 1'b0;
            ctrl3 = 1'b0;          
            ctrl5 = 1'b0;
            ctrl0 = 1'b0;
            ctrl1 = 1'b0;
            ctrl4 = 1'b0;
            ctrl6 = 1'b0;          
            count_w = 11'h000;         
            end
           else  if((frame_valid_1) && !(frame_valid_2))
                    begin
                    wen = 1'b1;                    
                    ctrl0=1'b1;  
                    count_w = 11'h000;
                    end                                                       
            else if (( line_valid_1 ) && !( line_valid_2 ))
                   begin
                    wen = 1'b0;
                    ctrl1 = 1'b1;                    
                    count_w = count_w +1;
                   end
            else if (( line_valid ) && (count_w <=11'h22f))
                   begin                   
                    count_w = count_w +1;                              
                    ctrl2 = 1'b1;                    
                   end
                                                                  
            else if (( line_valid )&&(count_w >=11'h22f)) 
                  begin
                   wen =1'b0;
                   count_w = count_w +1;
                   ctrl3   = 1'b1;
                   end

            else if(!( line_valid_1 ) && ( line_valid_2 ))
                 begin               
                    wen =1'b0;
                    ctrl4 = 1'b1;                   
                    count_w = 11'h000;                   
                 end
                                                        
            else if((ctrl4 == 1'b1)&&(count_w <= 11'h4ff))
                  begin
                  wen = 1'b0;
                  count_w = count_w + 1;
                  ctrl5 = 1'b1; 
                  end
            else begin 
                  wen   = 1'b1;                                
                  ctrl2 = 1'b0;
                  ctrl3 = 1'b0;               
                  ctrl5 = 1'b0;                 
                  count_w = 11'h000;                
                 end 

  always @(posedge clk_48 or negedge RESET )
    if (RESET== 1'b0 )
        begin
        ren =1'b1;
        count_r =10'h000;
        end
    else if (reset == 1'b0)
        begin
        ren =1'b1;
        count_r =10'h000;
        end
    else if((ctrl3 ==1'b1)&&(count_r < 10'h280))
        begin
        ren = 1'b0;
        count_r =count_r + 2;
        end
    else begin 
        ren = 1'b1;
        count_r = 10'h000;
        end
        
                    

  always @( * )	
    begin 
    case ( state )
        clear :
                if( ctrl0 ==1'b1 )
                    next_state = idle;
                else next_state = clear;
        idle   : 
                if( ctrl1 ==1'b1 )
                    next_state = start;
                else next_state =idle;

        start  :  
                if (ctrl2 == 1'b1 )                      
                    next_state = write;
                else next_state = start;
                
        write :
                
                 if(ctrl3 == 1'b1)
                    next_state = W_and_R;
                else next_state = write;
               
        W_and_R:        
            if(ctrl4 ==1'b1)
                    next_state = clear_start;
                else next_state = W_and_R;

        clear_start:
                if(ctrl5 ==1'b1)
                    next_state = clear;
                else next_state = clear_start; 
                
    endcase
    end 

	endmodule