📄 fpga_core.srr
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AO1_14_Y Net - - 0.655 - 3
fifo_data_inst.AO1_43 AO1 B In - 5.289 -
fifo_data_inst.AO1_43 AO1 Y Out 0.434 5.723 -
AO1_43_Y Net - - 0.841 - 4
fifo_data_inst.AO1_49 AO1 B In - 6.564 -
fifo_data_inst.AO1_49 AO1 Y Out 0.434 6.998 -
AO1_49_Y Net - - 0.469 - 2
fifo_data_inst.AO1_62 AO1 B In - 7.467 -
fifo_data_inst.AO1_62 AO1 Y Out 0.434 7.902 -
AO1_62_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 B In - 8.181 -
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 Y Out 0.691 8.871 -
RBINNXT_7_net Net - - 1.178 - 6
fifo_data_inst.XOR2_5 XNOR2 A In - 10.049 -
fifo_data_inst.XOR2_5 XNOR2 Y Out 0.366 10.415 -
XOR2_5_Y Net - - 0.469 - 2
fifo_data_inst.AND2_94 AND2 A In - 10.884 -
fifo_data_inst.AND2_94 AND2 Y Out 0.389 11.273 -
AND2_94_Y Net - - 0.469 - 2
fifo_data_inst.AO1_54 AO1 A In - 11.743 -
fifo_data_inst.AO1_54 AO1 Y Out 0.390 12.133 -
AO1_54_Y Net - - 0.279 - 1
fifo_data_inst.AO1_17 AO1 C In - 12.412 -
fifo_data_inst.AO1_17 AO1 Y Out 0.482 12.894 -
AO1_17_Y Net - - 0.469 - 2
fifo_data_inst.AO1_28 AO1 B In - 13.363 -
fifo_data_inst.AO1_28 AO1 Y Out 0.434 13.797 -
AO1_28_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 B In - 14.076 -
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 Y Out 0.691 14.767 -
RDIFF_10_net Net - - 0.841 - 4
fifo_data_inst.OA1C_0 OA1C C In - 15.608 -
fifo_data_inst.OA1C_0 OA1C Y Out 0.398 16.006 -
OA1C_0_Y Net - - 0.279 - 1
fifo_data_inst.NOR3_0 NOR3 C In - 16.285 -
fifo_data_inst.NOR3_0 NOR3 Y Out 0.552 16.837 -
NOR3_0_Y Net - - 0.279 - 1
fifo_data_inst.AO1_3 AO1 C In - 17.116 -
fifo_data_inst.AO1_3 AO1 Y Out 0.482 17.598 -
AO1_3_Y Net - - 0.279 - 1
fifo_data_inst.AOI1_0 AOI1 C In - 17.877 -
fifo_data_inst.AOI1_0 AOI1 Y Out 0.398 18.276 -
AOI1_0_Y Net - - 0.279 - 1
fifo_data_inst.DFN1P0_EMPTY DFN1P0 D In - 18.555 -
===================================================================================================
Total path delay (propagation time + setup) of 18.964 is 9.226(48.6%) logic and 9.739(51.4%) route.
Path information for path number 5:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 18.539
= Slack (non-critical) : -8.948
Number of logic level(s): 18
Starting point: fifo_data_inst.DFN1P0_EMPTY / Q
Ending point: fifo_data_inst.DFN1P0_EMPTY / D
The start point is clocked by fpga_core|clk_48 [rising] on pin CLK
The end point is clocked by fpga_core|clk_48 [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.483 0.483 -
empty Net - - 0.469 - 2
fifo_data_inst.NAND2_1 NAND2 A In - 0.953 -
fifo_data_inst.NAND2_1 NAND2 Y Out 0.389 1.342 -
NAND2_1_Y Net - - 0.279 - 1
fifo_data_inst.AND2_MEMORYRE NOR2A A In - 1.621 -
fifo_data_inst.AND2_MEMORYRE NOR2A Y Out 0.466 2.087 -
MEMORYRE Net - - 1.178 - 6
fifo_data_inst.AND2_40 AND2 B In - 3.264 -
fifo_data_inst.AND2_40 AND2 Y Out 0.466 3.730 -
AND2_40_Y Net - - 0.469 - 2
fifo_data_inst.AO1_14 AO1 B In - 4.199 -
fifo_data_inst.AO1_14 AO1 Y Out 0.434 4.634 -
AO1_14_Y Net - - 0.655 - 3
fifo_data_inst.AO1_43 AO1 B In - 5.289 -
fifo_data_inst.AO1_43 AO1 Y Out 0.434 5.723 -
AO1_43_Y Net - - 0.841 - 4
fifo_data_inst.AO1_49 AO1 B In - 6.564 -
fifo_data_inst.AO1_49 AO1 Y Out 0.434 6.998 -
AO1_49_Y Net - - 0.469 - 2
fifo_data_inst.AO1_62 AO1 B In - 7.467 -
fifo_data_inst.AO1_62 AO1 Y Out 0.434 7.902 -
AO1_62_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 B In - 8.181 -
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 Y Out 0.691 8.871 -
RBINNXT_7_net Net - - 1.178 - 6
fifo_data_inst.XOR2_5 XNOR2 A In - 10.049 -
fifo_data_inst.XOR2_5 XNOR2 Y Out 0.366 10.415 -
XOR2_5_Y Net - - 0.469 - 2
fifo_data_inst.AND2_94 AND2 A In - 10.884 -
fifo_data_inst.AND2_94 AND2 Y Out 0.389 11.273 -
AND2_94_Y Net - - 0.469 - 2
fifo_data_inst.AND2_97 AND2 B In - 11.743 -
fifo_data_inst.AND2_97 AND2 Y Out 0.466 12.209 -
AND2_97_Y Net - - 0.279 - 1
fifo_data_inst.AO1_17 AO1 A In - 12.488 -
fifo_data_inst.AO1_17 AO1 Y Out 0.390 12.878 -
AO1_17_Y Net - - 0.469 - 2
fifo_data_inst.AO1_28 AO1 B In - 13.347 -
fifo_data_inst.AO1_28 AO1 Y Out 0.434 13.781 -
AO1_28_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 B In - 14.060 -
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 Y Out 0.691 14.751 -
RDIFF_10_net Net - - 0.841 - 4
fifo_data_inst.OA1C_0 OA1C C In - 15.592 -
fifo_data_inst.OA1C_0 OA1C Y Out 0.398 15.990 -
OA1C_0_Y Net - - 0.279 - 1
fifo_data_inst.NOR3_0 NOR3 C In - 16.269 -
fifo_data_inst.NOR3_0 NOR3 Y Out 0.552 16.822 -
NOR3_0_Y Net - - 0.279 - 1
fifo_data_inst.AO1_3 AO1 C In - 17.100 -
fifo_data_inst.AO1_3 AO1 Y Out 0.482 17.582 -
AO1_3_Y Net - - 0.279 - 1
fifo_data_inst.AOI1_0 AOI1 C In - 17.861 -
fifo_data_inst.AOI1_0 AOI1 Y Out 0.398 18.260 -
AOI1_0_Y Net - - 0.279 - 1
fifo_data_inst.DFN1P0_EMPTY DFN1P0 D In - 18.539 -
===================================================================================================
Total path delay (propagation time + setup) of 18.948 is 9.210(48.6%) logic and 9.739(51.4%) route.
====================================
Detailed Report for Clock: fpga_core|clk_54
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------------------
wen fpga_core|clk_54 DFN1E0P0 Q wen 0.483 -10.338
fifo_data_inst.DFN1C0_FULL fpga_core|clk_54 DFN1C0 Q full 0.483 -9.827
fifo_data_inst.DFN1C0_WBIN_1_inst fpga_core|clk_54 DFN1C0 Q WBIN_1_net 0.483 -7.672
fifo_data_inst.DFN1C0_WBIN_0_inst fpga_core|clk_54 DFN1C0 Q WBIN_0_net 0.483 -7.629
fifo_data_inst.DFN1C0_WBIN_2_inst fpga_core|clk_54 DFN1C0 Q WBIN_2_net 0.483 -7.486
fifo_data_inst.DFN1C0_WBIN_3_inst fpga_core|clk_54 DFN1C0 Q WBIN_3_net 0.483 -7.420
fifo_data_inst.DFN1C0_RGRYSYNC_8_inst fpga_core|clk_54 DFN1C0 Q RGRYSYNC_8_net 0.483 -6.831
fifo_data_inst.DFN1C0_RGRYSYNC_9_inst fpga_core|clk_54 DFN1C0 Q RGRYSYNC_9_net 0.483 -6.722
fifo_data_inst.DFN1C0_RGRYSYNC_10_inst fpga_core|clk_54 DFN1C0 Q RGRYSYNC_10_net 0.483 -6.705
fifo_data_inst.DFN1C0_WBIN_4_inst fpga_core|clk_54 DFN1C0 Q WBIN_4_net 0.483 -6.664
============================================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1C0_FULL fpga_core|clk_54 DFN1C0 D AOI1_1_Y 9.690 -10.338
fifo_data_inst.DFN1C0_WGRY_10_inst fpga_core|clk_54 DFN1C0 D XOR2_8_Y 9.690 -2.401
fifo_data_inst.DFN1C0_WGRY_11_inst fpga_core|clk_54 DFN1C0 D XOR2_46_Y 9.590 -2.128
fifo_data_inst.DFN1C0_WGRY_9_inst fpga_core|clk_54 DFN1C0 D XOR2_39_Y 9.690 -2.025
fifo_data_inst.DFN1C0_WGRY_8_inst fpga_core|clk_54 DFN1C0 D XOR2_0_Y 9.690 -1.834
fifo_data_inst.DFN1C0_WGRY_6_inst fpga_core|clk_54 DFN1C0 D XOR2_95_Y 9.690 -1.648
fifo_data_inst.DFN1E1C0_MEM_WADDR_11_inst fpga_core|clk_54 DFN1E1C0 D XOR3_19_Y 9.590 -1.614
fifo_data_inst.DFN1C0_WBIN_11_inst fpga_core|clk_54 DFN1C0 D WBINNXT_11_net 9.690 -1.432
fifo_data_inst.DFN1C0_WGRY_7_inst fpga_core|clk_54 DFN1C0 D XOR2_99_Y 9.590 -1.375
fifo_data_inst.DFN1C0_WBIN_10_inst fpga_core|clk_54 DFN1C0 D WBINNXT_10_net 9.690 -1.055
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