📄 fpga_core.srr
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The end point is clocked by fpga_core|clk_48 [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.483 0.483 -
empty Net - - 0.469 - 2
fifo_data_inst.NAND2_1 NAND2 A In - 0.953 -
fifo_data_inst.NAND2_1 NAND2 Y Out 0.389 1.342 -
NAND2_1_Y Net - - 0.279 - 1
fifo_data_inst.AND2_MEMORYRE NOR2A A In - 1.621 -
fifo_data_inst.AND2_MEMORYRE NOR2A Y Out 0.466 2.087 -
MEMORYRE Net - - 1.178 - 6
fifo_data_inst.AND2_40 AND2 B In - 3.264 -
fifo_data_inst.AND2_40 AND2 Y Out 0.466 3.730 -
AND2_40_Y Net - - 0.469 - 2
fifo_data_inst.AO1_14 AO1 B In - 4.199 -
fifo_data_inst.AO1_14 AO1 Y Out 0.434 4.634 -
AO1_14_Y Net - - 0.655 - 3
fifo_data_inst.AO1_43 AO1 B In - 5.289 -
fifo_data_inst.AO1_43 AO1 Y Out 0.434 5.723 -
AO1_43_Y Net - - 0.841 - 4
fifo_data_inst.AO1_49 AO1 B In - 6.564 -
fifo_data_inst.AO1_49 AO1 Y Out 0.434 6.998 -
AO1_49_Y Net - - 0.469 - 2
fifo_data_inst.AO1_62 AO1 B In - 7.467 -
fifo_data_inst.AO1_62 AO1 Y Out 0.434 7.902 -
AO1_62_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 B In - 8.181 -
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 Y Out 0.691 8.871 -
RBINNXT_7_net Net - - 1.178 - 6
fifo_data_inst.XOR2_5 XNOR2 A In - 10.049 -
fifo_data_inst.XOR2_5 XNOR2 Y Out 0.366 10.415 -
XOR2_5_Y Net - - 0.469 - 2
fifo_data_inst.AND2_94 AND2 A In - 10.884 -
fifo_data_inst.AND2_94 AND2 Y Out 0.389 11.273 -
AND2_94_Y Net - - 0.469 - 2
fifo_data_inst.AND2_97 AND2 B In - 11.743 -
fifo_data_inst.AND2_97 AND2 Y Out 0.466 12.209 -
AND2_97_Y Net - - 0.279 - 1
fifo_data_inst.AO1_17 AO1 A In - 12.488 -
fifo_data_inst.AO1_17 AO1 Y Out 0.390 12.878 -
AO1_17_Y Net - - 0.469 - 2
fifo_data_inst.AO1_28 AO1 B In - 13.347 -
fifo_data_inst.AO1_28 AO1 Y Out 0.434 13.781 -
AO1_28_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 B In - 14.060 -
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 Y Out 0.691 14.751 -
RDIFF_10_net Net - - 0.841 - 4
fifo_data_inst.XNOR2_33 XNOR2 B In - 15.592 -
fifo_data_inst.XNOR2_33 XNOR2 Y Out 0.691 16.282 -
XNOR2_33_Y Net - - 0.279 - 1
fifo_data_inst.AND2_95 AND2 B In - 16.561 -
fifo_data_inst.AND2_95 AND2 Y Out 0.466 17.027 -
AND2_95_Y Net - - 0.279 - 1
fifo_data_inst.AO1_3 AO1 A In - 17.306 -
fifo_data_inst.AO1_3 AO1 Y Out 0.390 17.697 -
AO1_3_Y Net - - 0.279 - 1
fifo_data_inst.AOI1_0 AOI1 C In - 17.976 -
fifo_data_inst.AOI1_0 AOI1 Y Out 0.398 18.374 -
AOI1_0_Y Net - - 0.279 - 1
fifo_data_inst.DFN1P0_EMPTY DFN1P0 D In - 18.653 -
===================================================================================================
Total path delay (propagation time + setup) of 19.063 is 9.324(48.9%) logic and 9.739(51.1%) route.
Path information for path number 3:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 18.557
= Slack (non-critical) : -8.966
Number of logic level(s): 18
Starting point: fifo_data_inst.DFN1P0_EMPTY / Q
Ending point: fifo_data_inst.DFN1P0_EMPTY / D
The start point is clocked by fpga_core|clk_48 [rising] on pin CLK
The end point is clocked by fpga_core|clk_48 [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.483 0.483 -
empty Net - - 0.469 - 2
fifo_data_inst.NAND2_1 NAND2 A In - 0.953 -
fifo_data_inst.NAND2_1 NAND2 Y Out 0.389 1.342 -
NAND2_1_Y Net - - 0.279 - 1
fifo_data_inst.AND2_MEMORYRE NOR2A A In - 1.621 -
fifo_data_inst.AND2_MEMORYRE NOR2A Y Out 0.466 2.087 -
MEMORYRE Net - - 1.178 - 6
fifo_data_inst.AND2_40 AND2 B In - 3.264 -
fifo_data_inst.AND2_40 AND2 Y Out 0.466 3.730 -
AND2_40_Y Net - - 0.469 - 2
fifo_data_inst.AO1_14 AO1 B In - 4.199 -
fifo_data_inst.AO1_14 AO1 Y Out 0.434 4.634 -
AO1_14_Y Net - - 0.655 - 3
fifo_data_inst.AO1_43 AO1 B In - 5.289 -
fifo_data_inst.AO1_43 AO1 Y Out 0.434 5.723 -
AO1_43_Y Net - - 0.841 - 4
fifo_data_inst.AO1_49 AO1 B In - 6.564 -
fifo_data_inst.AO1_49 AO1 Y Out 0.434 6.998 -
AO1_49_Y Net - - 0.469 - 2
fifo_data_inst.AO1_62 AO1 B In - 7.467 -
fifo_data_inst.AO1_62 AO1 Y Out 0.434 7.902 -
AO1_62_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 B In - 8.181 -
fifo_data_inst.XOR2_RBINNXT_7_inst XOR2 Y Out 0.691 8.871 -
RBINNXT_7_net Net - - 1.178 - 6
fifo_data_inst.AND2_7 NOR2A B In - 10.049 -
fifo_data_inst.AND2_7 NOR2A Y Out 0.308 10.357 -
AND2_7_Y Net - - 0.469 - 2
fifo_data_inst.AO1_34 AO1 B In - 10.826 -
fifo_data_inst.AO1_34 AO1 Y Out 0.434 11.260 -
AO1_34_Y Net - - 0.279 - 1
fifo_data_inst.AO1_54 AO1 C In - 11.539 -
fifo_data_inst.AO1_54 AO1 Y Out 0.482 12.021 -
AO1_54_Y Net - - 0.279 - 1
fifo_data_inst.AO1_17 AO1 C In - 12.300 -
fifo_data_inst.AO1_17 AO1 Y Out 0.482 12.782 -
AO1_17_Y Net - - 0.469 - 2
fifo_data_inst.AO1_28 AO1 B In - 13.251 -
fifo_data_inst.AO1_28 AO1 Y Out 0.434 13.685 -
AO1_28_Y Net - - 0.279 - 1
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 B In - 13.964 -
fifo_data_inst.XOR2_RDIFF_10_inst XOR2 Y Out 0.691 14.655 -
RDIFF_10_net Net - - 0.841 - 4
fifo_data_inst.XNOR2_33 XNOR2 B In - 15.496 -
fifo_data_inst.XNOR2_33 XNOR2 Y Out 0.691 16.186 -
XNOR2_33_Y Net - - 0.279 - 1
fifo_data_inst.AND2_95 AND2 B In - 16.465 -
fifo_data_inst.AND2_95 AND2 Y Out 0.466 16.931 -
AND2_95_Y Net - - 0.279 - 1
fifo_data_inst.AO1_3 AO1 A In - 17.210 -
fifo_data_inst.AO1_3 AO1 Y Out 0.390 17.600 -
AO1_3_Y Net - - 0.279 - 1
fifo_data_inst.AOI1_0 AOI1 C In - 17.879 -
fifo_data_inst.AOI1_0 AOI1 Y Out 0.398 18.278 -
AOI1_0_Y Net - - 0.279 - 1
fifo_data_inst.DFN1P0_EMPTY DFN1P0 D In - 18.557 -
===================================================================================================
Total path delay (propagation time + setup) of 18.967 is 9.418(49.7%) logic and 9.548(50.3%) route.
Path information for path number 4:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 18.555
= Slack (non-critical) : -8.964
Number of logic level(s): 18
Starting point: fifo_data_inst.DFN1P0_EMPTY / Q
Ending point: fifo_data_inst.DFN1P0_EMPTY / D
The start point is clocked by fpga_core|clk_48 [rising] on pin CLK
The end point is clocked by fpga_core|clk_48 [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
fifo_data_inst.DFN1P0_EMPTY DFN1P0 Q Out 0.483 0.483 -
empty Net - - 0.469 - 2
fifo_data_inst.NAND2_1 NAND2 A In - 0.953 -
fifo_data_inst.NAND2_1 NAND2 Y Out 0.389 1.342 -
NAND2_1_Y Net - - 0.279 - 1
fifo_data_inst.AND2_MEMORYRE NOR2A A In - 1.621 -
fifo_data_inst.AND2_MEMORYRE NOR2A Y Out 0.466 2.087 -
MEMORYRE Net - - 1.178 - 6
fifo_data_inst.AND2_40 AND2 B In - 3.264 -
fifo_data_inst.AND2_40 AND2 Y Out 0.466 3.730 -
AND2_40_Y Net - - 0.469 - 2
fifo_data_inst.AO1_14 AO1 B In - 4.199 -
fifo_data_inst.AO1_14 AO1 Y Out 0.434 4.634 -
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